STNRGPF02 datasheet(20/43 Pages) STMICROELECTRONICS

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TYPE(1)

NAME

STNRGPF12

NAME

STNRGPF02

PIN DESCRIPTION

SIN_REF

This pin generates a PWM signal with sinusoidal duty

cycle. This PWM signal must be filtered in order to have

the current sinusoidal reference that is synchronized with

input voltage mains.

SET_O

This pin generates a pulse in order to trigger set ON the

CH1 channel with the right out of phase. This pin must be

connected to pin 18

ENABLE

This pin receive the CLOCK signal in order to avoid

undesired commutation

SYNCR[2]

This pin receives the PWM0 signal in order to synchronize

the others channels. The falling edge of PWM0 signal is

used to trigger OFF the slave channels CH1 and CH2

SCR[0]

RES[2]

STNRGPF12: This pin generates the PWM signal in order

to drive one of the two switches in the input semicontrolled

bridge to performs the Inrush Current Limiter feature. The

switch can be an SCR. STNRGPF02: Reserved

RES[0]

Reserved

RES[1]

Reserved

VDD

Supply Voltage

VSS

Ground

VOUT

Supply Voltage of digital section. An external capacitor

must be connected to VOUT pin.

PFC_FAULT

During normal operation this pin is high. If a fault condition

happens it’s forced low.

PFC_OK

During fault condition this pin is high. When the PFC is

ready for load connection it’s forced low.

PWM[1]

This pin generates the PWM for the channel CH1

ZVD

This pin receives a square wave signal synchronized with

input AC voltage. The rising edge of square wave signal is

used by the STNRGPF12 to detect the ZVD instant.

SET_I

This pin receives a pulse in order to trigger ON the CH1

channel. This pin must be connected to pin 5

OCP

During normal operation this pin is high. If an overcurrent

occurs, it's forced low instantaneously

FAN

It generates a CMOS/TTL signal that is low until the PFC

output power is below a threshold defined during device

customization

SCR[1]

RELAY

STNRGPF12: This pin generates the PWM signal in order

to drive one of the two switches in the input semicontrolled

bridge to performs the Inrush Current Limiter feature. The

switch can be an SCR. STNRGPF02: It generates a signal

that is low during the inrush phase. As soon as the inrush

phase is completed this signal became high and it can be

used to short the limiter resistor or to disable any current

limiter apparatus

PTX

Programming data transmit

PRX

Programming data receive

OUT_PI[3]

Positive input of internal analog comparator 3. It receives

the out of analog PI current

OUT_PI[2]

Positive input of internal analog comparator 3. It receives

the out of analog PI current

STNRGPF02, STNRGPF12

Pin description

DS12895 - Rev 2

page 20/43

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