ORG4572-R01-UAR datasheet(26/40 Pages) ETC

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Multi Spider - ORG4572 Datasheet

Revision 3.0

November 23, 2014

17.5. DATA INTERFACE

ORG4572 module has 3 types of interface ports to connect to host - UART, SPI or I²C – all multiplexed

on a shared set of pads. At system reset host port interface lines are disabled, so no conflict occurs.

Logic values on CTS

̅̅̅̅̅ and RTS

̅̅̅̅̅ are read by the module during startup and define host port type.

External resistor of 10kΩ is recommended. Pull-up resistor is referenced to 1.8V.

PORT TYPE

CTS

̅̅̅̅̅

RTS

̅̅̅̅̅

UART

External pull-up

Internal pull-up

SPI (default)

Internal pull-down

Internal pull-up

I²C

Internal pull-down

External pull-down

TABLE 11 – HOST INTERFACE SELECT

17.5.1. UART

Multi Spider ORG4572 has a standard UART port:

TX used for GNSS data reports. Output logic high voltage level is LVCMOS 1.8V compatible.

RX used for receiver control. Input logic high voltage level is 1.45V tolerable up to 3.6V.

UART flow control using CTS

̅̅̅̅̅ and RTS

̅̅̅̅̅ lines is disabled by default.

Can be turned on by sending OSP® Message ID 178, Sub ID 2 input command.

17.5.2. UART BAUD RATE AND PROTOCOL SELECTION

Logic values on GPIO1 and GPIO2 are read by the module during startup and define UART baud

rate and protocol. Internal pull-up resistors set default protocol to NMEA @ 4,800bps.

Those resistors are 2.2kΩ each and referenced to 1.8V.

External straps of 0Ω, or temporary assertions prior to startup can be used to override defaults.

PROTOCOL

BAUD RATE

GPIO1

GPIO2

NMEA (default)

4,800 (default)

Internal pull-up

NMEA

9,600

Internal pull-up

External strap

NMEA

38,400

External strap

Internal pull-up

OSP®

115,200

External strap

TABLE 12 – UART BAUD RATE AND PROTOCOL SELECT

17.5.3. SPI

SPI host interface features are:

Slave SPI Mode 1, supports clock up to 6.8MHz.

RX and TX have independent 2-byte idle patterns of ‘0xA7 0xB4’.

TX and RX each have independent 1024 byte FIFO buffers.

TX FIFO is disabled when empty and transmits its idle pattern until re-enabled.

RX FIFO detects a software specified number of idle pattern repeats and then disables FIFO

input until the idle pattern is broken.

FIFO buffers can generate an interrupt at any fill level.

SPI detects synchronization errors and can be reset by software.

Output is LVCMOS 1.8V compatible. Inputs are tolerable up to 3.6V.

17.5.4. I²C

I²C host interface features are:

2C Multi-Master Mode - module initiates clock and data, operating speed 400kbps.

2C address ‘0x60’ for RX and ‘0x62’ for TX.

Individual transmit and receive FIFO length of 64 bytes.

2C host interface mode can be switched slave (Multi-master default), clock rate can be

switched 100KHz (default 400KHz), address can be changed (default 0x62 for TX FIFO and

0x60 for RX FIFO) by sending OSP® Message ID 178, Sub ID 2 input command.

SCL and SDA are pseudo open-drain lines, therefore require external pull-up resistors of

2.2kΩ to 1.8V, or 3.3kΩ to 3.3V.

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