List of figures

Figure 1.

Pin connections (top view) ............................................................ 2

Figure 2.

Pin connections (top view) ............................................................ 2

Figure 3.

Supply current vs. supply voltage ...................................................... 10

Figure 4.

Input offset voltage distribution at VCC = 5 V TSB7191A, TSB7192A .............................. 10

Figure 5.

Input offset voltage distribution at VCC = 36 V TSB7191A, TSB7192A ............................. 10

Figure 6.

Input offset voltage vs. temperature at VCC = 5 V ........................................... 10

Figure 7.

Input offset voltage vs. temperature at VCC = 36 V .......................................... 11

Figure 8.

Input offset voltage thermal coefficient distribution at VCC = 5 V ................................. 11

Figure 9.

Input offset voltage vs. supply voltage ................................................... 11

Figure 10.

Input offset voltage vs. common mode voltage at VCC = 5 V .................................... 11

Figure 11.

Input offset voltage vs. common mode voltage at VCC = 36 V ................................... 11

Figure 12.

Input bias current vs. temperature at VICM = VCC / 2 ......................................... 11

Figure 13.

Output current vs. output voltage at

VCC = 5 V ....................................... 12

Figure 14.

Input bias current vs. common mode voltage at VCC = 5 V ..................................... 12

Figure 15.

Input bias current vs. common mode voltage at VCC = 36 V .................................... 12

Figure 16.

Output current vs. output voltage at VCC = 36 V ............................................ 12

Figure 17.

Output voltage (VOH) vs. supply voltage.................................................. 12

Figure 18.

Output voltage (VOL) vs. supply voltage .................................................. 12

Figure 19.

Positive slew rate at VCC = 36 V ....................................................... 13

Figure 20.

Negative slew rate at VCC = 36 V ...................................................... 13

Figure 21.

Bode diagram at VCC = 5 V .......................................................... 13

Figure 22.

Bode diagram at VCC = 36 V ......................................................... 13

Figure 23.

Phase margin vs. output current at VCC = 5 V .............................................. 13

Figure 24.

Phase margin vs. output current at VCC = 36 V ............................................. 13

Figure 25.

Phase margin vs. capacitive load ...................................................... 14

Figure 26.

Small step response vs. time at VCC = 5 V ................................................ 14

Figure 27.

Desaturation time at low rail at VCC = 5 V................................................. 14

Figure 28.

Desaturation time at high rail at VCC = 5 V ................................................ 14

Figure 29.

Small step response vs. time at VCC = 36 V ............................................... 14

Figure 30.

Amplifier behavior close to the low rail at VCC = 36 V......................................... 14

Figure 31.

Amplifier behavior close to the high rail at VCC = 36 V ........................................ 15

Figure 32.

Noise vs. frequency at VCC = 5 V ...................................................... 15

Figure 33.

Noise vs. frequency at VCC = 36 V ..................................................... 15

Figure 34.

Noise vs. time at VCC = 36 V ......................................................... 15

Figure 35.

THD+N vs. frequency .............................................................. 15

Figure 36.

THD+N vs. output voltage ........................................................... 15

Figure 37.

PSRR vs. frequency at VCC = 10 V ..................................................... 16

Figure 38.

CMRR vs. frequency at VCC = 10 V..................................................... 16

Figure 39.

Channel separation vs. frequency at VCC = 36 V............................................ 16

Figure 40.

Input current limitation .............................................................. 17

Figure 41.

Rail-to-rail input stage .............................................................. 18

Figure 42.

EMIRR on In+, In- and out pins........................................................ 20

Figure 43.

Proposed circuit configuration for unity gain stability ......................................... 21

Figure 44.

Small step response vs. time in follower configuration ........................................ 21

Figure 45.

Small step response vs. time in the proposed compensated circuit configuration ...................... 21

Figure 46.

Low-side current sensing schematic .................................................... 23

Figure 47.

SOT23-5 package outline ........................................................... 24

Figure 48.

MiniSO8 package outline ............................................................ 26

TSB7191, TSB7191A, TSB7192, TSB7192A

List of figures

DS12641 - Rev 5

page 32/34