AM652X datasheet(250/284 Pages) TI

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8.3 Accelerators and Coprocessors

8.3.1 PRU_ICSSG

The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)

consists of:

• Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)

• Two auxiliary 32-bit load/store RISC CPU cores — Auxiliary Programmable Real-Time Units (RTU_PRU0 and

RTU_PRU1)

• Data RAMs per PRU core

• Instruction RAMs per PRU and per RTU_PRU cores

• Shared RAM

• Peripheral modules: UART0, ECAP0, PWM, IEP0 and IEP1

• Interrupt controller (INTC)

The programmable nature of the PRU cores, along with their access to pins, events and all device resources,

provides flexibility in implementing fast real-time responses, specialized data handling operations, custom

peripheral interfaces, and in offloading tasks from the other processor cores of the device.

The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate

independently or in coordination with each other and can also work in coordination with the device-level host

CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU’s

instruction memory.

8.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores

The PRU is a processor optimized for performing embedded tasks that require manipulation of packed memory

mapped data structures, handling of system events that have tight real-time constraints and interfacing with

systems external to the SoC. The PRU is both very small and very efficient at handling such tasks.

8.3.1.2 PRU_ICSSG Broadside Accelerators Overview

The PRU_ICSSG supports a broadside interface, which uses the XFR (XIN, XOUT, or XCHG) instruction

to transfer the contents of PRUn or RTU_PRUn (where n = 0 or 1) registers to or from accelerators with

the PRU_ICSSG. This interface enables up to 31 registers (R0-R30, or 124 bytes) to be transferred in a

single instruction. The PRU_ICSSG broadside accelerators are divided into two categories – data processing

accelerators and data movement accelerators.

8.3.1.3 PRU_ICSSG UART Module

The PRU_ICSSG UART0 peripheral is based on the industry standard TL16C550 asynchronous

communications element, which in turn is a functional upgrade of the TL16C450.

The PRU_ICSSG UART0 performs serial-to-parallel conversions on data received from a peripheral device and

parallel-to-serial conversion on data received from the CPU. The CPU can read the PRU_ICSSG UART0 status

at any time. The PRU_ICSSG UART0 includes control capability and a processor interrupt system that can be

tailored to minimize software management of the communications link.

8.3.1.4 PRU_ICSSG ECAP Module

A single instance of an Enhanced Capture event module (ECAP0) is integrated in each device PRU_ICSSG0,

PRU_ICSSG1 and PRU_ICSSG2 subsystem.

This module provides accurate timing of events. When not being used for event capture, its resources can be

used to generate a single channel of asymmetrical PWM waveforms (configurable as either one capture input, or

as one auxiliary PWM output).

8.3.1.5 PRU_ICSSG PWM Module

Each of the PRU_ICSSG modules integrates one Pulse Width Modulation module (PWM). The PWM module

uses the PRU_ICSSG IEP0 and IEP1 compare events to produce the PWM outputs.

AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

www.ti.com

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