AM652X datasheet(246/284 Pages) TI

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7.9.5.25 Emulation and Debug

7.9.5.25.1 Debug Trace

Table 7-79 and Figure 7-124 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 7-78. Debug Trace Timing Conditions

PARAMETER

MIN

MAX

UNIT

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Mismatch)

Propagation delay mismatch across

all traces

200

Table 7-79. Debug Trace Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

DBTR1

tc(TRC_CLK)

Cycle time, TRC_CLK

10.16

DBTR2

tw(TRC_CLKH)

Pulse width, TRC_CLK high

4.33

DBTR3

tw(TRC_CLKL)

Pulse width, TRC_CLK low

4.33

DBTR4

tosu(TRC_DATAV-

TRC_CLK)

Output setup time, TRC_DATA valid to TRC_CLK edge

1.27

DBTR5

toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid

1.27

DBTR6

tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge

1.27

DBTR7

toh(TRC_CLK-TRC_CTLI)

Output hold time, TRC_CLK edge to TRC_CTL invalid

1.27

TRC_DATA

TRC_CTL

TRC_CLK

(

)

(

)

(Ideal)

Worst Case 1

Worst Case 2

DBTR1

DBTR2

DBTR3

DBTR4

DBTR6

DBTR5

DBTR7

DBTR4

DBTR6

DBTR5

DBTR7

SPRSP08_Debug_01

Figure 7-124. Debug Trace Switching Characteristics

7.9.5.25.2 JTAG

For more details about features and additional description information on the device IEEE 1149.1 Standard-Test-

Access Port, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed

Description.

Table 7-80 presents the timing conditions for JTAG.

Table 7-80. JTAG Timing Conditions

PARAMETER

SIGNAL

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

TCK

0.5

2.00

V/ns

TDI, TMS

0.25

2.00

V/ns

OUTPUT CONDITIONS

Output load capacitance

TDO

AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

www.ti.com

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