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AM652X Folha de dados(PDF) 234 Page - Texas Instruments

Nome de Peças AM652X
Descrição Electrónicos  AM654x, AM652x Sitara™ Processors Silicon Revision 2.1
PDF  284 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

AM652X Folha de dados(HTML) 234 Page - Texas Instruments

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NO.
DESCRIPTION
MIN
MAX UNIT
PRPIF4 td(PIF_CLK-PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN
-5
5 ns
(1)
P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the ICSSG_PRUn_ED_TX_CFG_REG,
where n = 0 or 1.
PIF_CLK
PIF_DATA_OUT
PRPIF1
PRPIF2H
PRPIF3
SPRSP08_TIMING_PIF_02
PRPIF2L
PIF_DATA_EN
PRPIF4
Figure 7-103. PRU_ICSSG PRU Peripheral Interface Switching Characteristics
7.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
7.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
Table 7-72 presents the PRU_ICSSG PWM timing conditions.
Table 7-72. PRU_ICSSG PWM Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
1
4
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
2
7
pF
7.9.5.21.2.1.1 PRU_ICSSG PWM Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRPWM1 tsk(PWM_A/B)
PWM_A/B skew
5
ns
PWM_A/B
SPRSP08_TIMING_PRU_PWM_01
PRPWM1
Figure 7-104. PRU_ICSSG PRU PWM Timing
7.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
7.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
7.9.5.21.3.1.1 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
NO.
MIN
MAX
UNIT
PRIEP1 tw(EDC_SYNCx_OUTL)
Pulse Duration, EDC_SYNCx_OUT Low
-2+20×P
(1)
ns
PRIEP2 tw(EDC_SYNCx_OUTH)
Pulse Duration, EDC_SYNCx_OUT High
-2+20×P
(1)
ns
AM6548, AM6528, AM6546, AM6526
SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021
www.ti.com
234
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Product Folder Links: AM6548 AM6528 AM6546 AM6526



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