CC1070-RTR1 datasheet(30/57 Pages) TI

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CC1070

SWRS043

Page 30 of 58

14.2 VCO and PLL Self-Calibration

compensate

for

supply

voltage,

temperature and process variations, the

VCO and PLL must be calibrated. The

calibration is performed automatically and

sets the maximum VCO tuning range and

optimum charge pump current for PLL

stability. After setting up the device at the

operating frequency, the self-calibration

can

initiated

setting

the

CAL_START bit in the CALIBRATE

internally in the chip, and is valid as long

as power is not turned off. If large supply

voltage drops (typically more than 0.25 V)

or temperature variations (typically more

than 40

oC) occur after calibration, a new

calibration should be performed.

The nominal VCO control voltage is set by

the

CAL_ITERATE[2:0]

bits

the

CALIBRATE register.

The CAL_COMPLETE bit in the STATUS

finished.

The

calibration

wait

time

(CAL_WAIT) is programmable and is

proportional to the internal PLL reference

frequency. The highest possible reference

frequency should be used to get the

minimum

calibration

time.

recommended to use CAL_WAIT[1:0] = 11

in order to get the most accurate loop

bandwidth.

The CAL_COMPLETE bit can also be

monitored at the LOCK pin, configured by

LOCK_SELECT[3:0] = 0101, and used as

an interrupt input to the microcontroller.

To check that the PLL is in lock the user

should monitor the LOCK_CONTINUOUS

bit

the

STATUS

The

LOCK_CONTINUOUS bit can also be

monitored at the LOCK pin, configured by

LOCK_SELECT[3:0] = 0010.

There are separate calibration values for

the two frequency registers. However,

dual calibration is possible if all of the

below conditions apply:

•

The two frequencies A and B differ by

less than 1 MHz

•

Reference

frequencies

are

equal

(REF_DIV_A[2:0] = REF_DIV_B[2:0]

in the CLOCK_A/CLOCK_B registers)

•

VCO

currents

are

equal

(VCO_CURRENT_A[3:0]

VCO_CURRENT_B[3:0] in the VCO

The CAL_DUAL bit in the CALIBRATE

controls

dual

separate

calibration.

The

single

calibration

algorithm

(CAL_DUAL = 0) is illustrated in Figure 17.

The same algorithm is applicable for dual

calibration if CAL_DUAL = 1.

Chipcon

recommends

that

single

calibration be used for more robust

operation.

There is a small, but finite, possibility that

the PLL self-calibration will fail. The

calibration routine in the source code

should include a loop so that the PLL is re-

calibrated until PLL lock is achieved if the

PLL does not lock the first time. Refer to

CC1070 Errata Note 001.

The CAL_SELECT bit is used to select the

calibration routine. When set high, a fast

calibration routine is used.

The table below shows the calibration time

when CAL_SELECT = 1:

Calibration

time [ms]

Reference frequency [MHz]

CAL_WAIT

7.3728

1.0

1.5

2.9

3.9

Table 18. Typical calibration time when

CAL_SELECT = 1

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