MPFS160T datasheet(30/50 Pages) MICROCHIP

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4.3.1.5

Reference Clock

The reference clock pins allow connections directly with the transceiver lane quads. The reference clock inputs

provide flexibility to interface with both single-ended and differential clocks, and can drive up to two independent

clocks per transceiver lane quad. These reference clocks can also be sources for the global and regional clock

networks in the FPGA fabric of the device.

The following illustration shows the connectivity between the reference clock and transceiver lane quads.

Figure 4-3. Reference Clock

CMOS

DIFF

Termination

SERDES_VREF

SERDES_REFCLK_P

SERDES_REFCLK_N

RefClk

Interface

Refclk0

Refclk1

VDDSREF

Filter

Internal

Reference

Voltage

Circuit

4.3.1.6

Quad Lane Overlay Assignments

The transceiver lane either connects the parallel side of the interface to the PCIe Gen2 controller or to the fabric.

The PCIe connections are fixed in the hardware and have a dedicated number of combinations between the two

controllers. The fabric interface is used to support the PMA, 8b/10b, 64b/6xb, and PIPE modes and have complete

flexibility into the fabric connections.

For detailed lane assignments, see UG0920: PolarFire SoC FPGA PCI Express User Guide.

4.3.2

Inputs/Outputs

PolarFire SoC FPGA I/Os are grouped into pairs to meet the differential I/O standards. Additionally, they are grouped

in lanes of 12 buffers with a lane controller for memory interfaces, as shown in the following illustration.

Programmable Logic Subsystem

and its subsidiaries

Overview

DS60001656C-page 30

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