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AM2434...ALV Folha de dados(PDF) 126 Page - Texas Instruments |
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AM2434...ALV Folha de dados(HTML) 126 Page - Texas Instruments |
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126 / 280 page  7.7.7 ADC12B Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VADC0_VREFP (1) Positive Reference Voltage, ADC0_VREFP 1.71 1.89 V VADC0_VREFN (1) Negative Reference Voltage, ADC0_VREFN VSS V VADC_AIN[7:0] Analog Input Voltage, ADC_AIN[7:0], Full-scale VSS VDDA_ADC0 V DNL Differential Non-Linearity > -1 +1 LSB INL Integral Non-Linearity -2 +2 LSB LSBGAIN-ERROR Gain Error ±10 LSB LSBOFFSET-ERROR Offset Error ±5 LSB SNR Signal-to-Noise Ratio Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 70 dB THD Total Harmonic Distortion Input Signal: 200 kHz sine wave at -0.5 dB Full Scale -75 dB ZADC_AIN[0:7] Analog Input Impedance, ADC0_AIN[7:0] (2) Ω IIN Input Leakage ±10 μA CSMPL Sampling Capacitance 5.5 pF Sampling Dynamics FSMPL_CLK ADC0 SMPL_CLK Frequency 60 MHz tC Conversion Time 13 ADC0 SMPL_CLK Cycles tACQ Acquisition Time 2 257 ADC0 SMPL_CLK Cycles TR Sampling Rate ADC0 SMPL_CLK = 60 MHz 4 MSPS General Purpose Input Mode (3) VIL Input Low Voltage 0.35 × VDDA_ADC0 V VILSS Input Low Voltage Steady State 0.35 × VDDA_ADC0 V VIH Input High Voltage 0.65 × VDDA_ADC0 V VIHSS Input High Voltage Steady State 0.65 × VDDA_ADC0 V VHYS Input Hysteresis Voltage 200 mV II Input Leakage Current ADC0_AIN[7:0] = VDDA_ADC0 or ADC0_AIN[7:0] = VSS 2 μA (1) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails. ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is connected to a power source capable of providing at least 4 mA of current. ADC0_REFP can be connected to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency decoupling capacitor must be connected directly to the ADC0_REFP and ADC0_REFN pins with vias and be placed in the ball array on the back side of the PCB. (2) The ADC0_AIN pins are connected to an internal sampling capacitor for a user configurable acquisition time and acquisition frequency. The input impedance of the ADC0_AIN pins is a function of the sampling capacitance along with user configurable acquisition time and AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 www.ti.com 126 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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