AM6422...ALV datasheet(5/244 Pages) TI

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3.1 Functional Block Diagram

Figure 3-1 is functional block diagram for the device.

Note

To understand what device features are currently supported by TI Software Development Kits (SDKs),

see the AM64x Software Build Sheet.

Industrial Connectivity

PRU-ICSS(Gb)

System Memory

Security

A 64x

intro_001

2x Arm®

Cortex -A53

256KB L2 with ECC

Arm

Cortex -A53

128KB TCM

Arm

Cortex -R5F

Arm

Cortex -A53

128KB TCM

Arm

Cortex -R5F

Arm

Cortex -R5F

Arm

Cortex -R5F

Arm

Cortex -M4F

256KB SRAM

2 MB SRAM with ECC

DDR4/LPDDR4 with inline ECC

2x MMCSD

AES

MD5

SHA

3DES

PKA

DRBG

Secure

Boot

System Services

12x GP Timers

4x WWDT

Sync

Manager

3x EQEP

3x ECAP

9x EPWM

4x I2C

GPIO

5x MCSPI

1x ADC

7x UART

PCIe

(C)

1x Single lane

Gen 2

GPMC / ELM

8x FSI

OSPI or QSPI

2x CAN-FD

2x GMAC

Encoder

with 9x

∆

∑

PRU-ICSS(Gb)

2x GMAC

Encoder

with 9x

∆

∑

1x USB 3.1 DRD

(C)

3-port Gb

Ethernet

(B)

General Connectivity

2x I2C

GPIO

2x MCSPI

2x UART

Isolated Connectivity

(A)

(for use with Cortex-M4F)

Application cores

Real-time cores

Isolated core

(A)

Isolation of peripherals and M4F core is an optional feature. MCU domain resources are shared across SoC when in non-isolated

configuration.

One port is internally connected only; not connected to any pins.

USB3.1 and PCIe share a common SerDes lanes.

Figure 3-1. Functional Block Diagram

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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