RZ_G2UL datasheet(44/83 Pages) RENESAS

Nome de Peças	RZ_G2UL

Descrição Electrónicos	RZ/G2UL, RZ/A3UL, RZ/Five SMARC Module Board

PDF	83 Pages

Scroll/Zoom	100%

Fabricante Electrônico	RENESAS [Renesas Technology Corp]

Página de início	http://www.renesas.com

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RZ Family / RZ/G, RZ/A Series

2. Functional Specifications

R01UH0990EJ0101

Rev.1.01

Page 44 of 83

Jul 28, 2022

2.3.2

DDR4 SDRAM

Figure 2.2 shows a block diagram of the DDR4 SDRAM interface.

The DDR4 SDRAM is controlled by the DDR3L/DDR4 SDRAM Memory Controller (MEMC) that is with built-in to

the RZ/G2UL. This interface supports up to DDR4-1600 SDRAM, a data bus width of 16-bit and inline ECC.

This interface complies with JEDEC STANDARD JESD79-4C.

Figure 2.2

Block Diagram of DDR4 SDRAM

DDR_CLK_N

DDR_CLK_P

R13

DDR_ADDR15

DDR_ADDR11

DDR_ADDR2

DDR_ADDR10

DDR_BA0

DDR_ADDR14

DDR_ADDR5

DDR_CAS#

DDR_ADDR3

DDR_ADDR6

DDR_ADDR8

DDR_BA2

DDR_WE#

DDR_ADDR7

DDR_ADDR0

DDR_ADDR12

DDR_ADDR9

DDR_CS0#

DDR_BA1

DDR_ADDR1

DDR_ADDR4

DDR_ADDR13

DDR_RESET#

DDR_ODT0

DDR_CKE

DDR_CLK_N

DDR_CLK_P

DDR_DQ1

DDR_DQ3

DDR_DQ7

DDR_DQ2

DDR_DQ5

DDR_DQ0

DDR_DQ4

DDR_DQ6

DDR_DQS0_P

DDR_DQS0_N

DDR_DM0

DDR_DQ12

DDR_DQ11

DDR_DQ15

DDR_DQ13

DDR_DQ14

DDR_DQ9

DDR_DQ8

DDR_DQ10

DDR_DQS1_P

DDR_DQS1_N

DDR_DM1

RZ/G2UL, RZ/A3UL, RZ/Five

RZ/A3UL SMARC Module Board

OCTAL Edition

RZ/A3UL SMARC Module Board

QSPI Edition

RZ/G2UL SMARC Module Board

RZ/Five SMARC Module Board

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