ADP1034ACPZ-1-R7 datasheet(7/41 Pages) AD

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Data Sheet

ADP1034

SPECIFICATIONS

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Rev. 0 | 7 of 41

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SPI

Output Rise Time/Fall Time

tR/tF

10% to 90%

Common-Mode Transient Immunity8

|CM|

100

kV/µs

1 VIx is the Channel x logic input, where Channel x can be MCK, MO, SO, SGPI1, MGPI2, or SGPI3.

2 VxVDD is either VMVDD or VSVDDx depending on whether the input side is master or slave.

3 VINPUT is the voltage at the input of the digital pins.

4 IOx is the output current of the pin.

5 VIxH is the input side logic high.

6 VIxL is the input side logic low.

7 VOx is the voltage where the output is pulled.

8 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 MVDD and/or SVDDx. The common-mode voltage slew rates

apply to both rising and falling common-mode voltage edges.

TIMING CHARACTERISTICS

1-Wire Serial Interface Timing Specifications

VVINP = 24 V, VMVDD = 3.3 V, VSVDDx = 3.3 V, VOUT1 = 24 V, VOUT2 = 5 V, VOUT3 = −15 V, and TA = 25°C for typical specifications. Minimum and

maximum specification apply over the entire operating range of 4.5 V ≤ VVINP ≤ 60 V, 2.3 V ≤ VMVDD ≤ 5.5 V, 1.8 V ≤ VSVDDx ≤ 5.5 V, and −40°C

≤ TJ ≤ +125°C, unless otherwise noted. Refer to the 1-Wire Serial Interface section for more information on the 1-wire serial interface.

Table 2. 1-Wire Serial Interface

Parameter1, 2

Description

Min

Typ

Max

Unit

Test Conditions / Comments

tPPC_TOTAL_RES

Response time

PPC transaction time plus VOUT1 settling time

from 6 V to 28 V

tPPC1

Bit period

4500

5000

6600

tPPC2

Start detect high time

200

400

tPPC3

Start detect low time

200

400

tPPC4

Start detect sample time

900

1000

1100

Time for two consecutive pulses

tPPC5

Logic low time

400

800

tPPC6

Logic high time

1200

3500

4400

tPPC7

Slave pull down window

2200

2700

Time window for slave to control the bus

during acknowledge or parity

tPPC8

Time when the master takes back control of the bus when there is

no response from the slave

3400

3600

tPPC9

Time when the master takes back control of the bus when the

slave responds by pulling low

2727

tLP

Bus lockup protection

1350

1500

1650

Analog watchdog timer

1 All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of the voltage on the VOUT2 pin (VOUT2) and timed from a voltage level of VOUT2/2.

2 Guaranteed by design and characterization; not production tested.

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