AZC199-04C

Low Capacitance High ESD Level Protection Array

For High Speed I/O Port

Revision 2011/07/30

©2011-2012 Amazing Micro.

5

www.amazingIC.com

B. Device Connection

The AZC199-04C is designed to protect four

data

lines

and

power

rails

from

transient

over-voltage (such as ESD stress pulse). The

device connection of AZC199-04C is shown in

the Fig. 2. In Fig. 2, the four protected data lines

are connected to the ESD protection pins (pin1,

pin3, pin4, and pin6) of AZC199-04C. The

ground pin (pin2) of AZC199-04C is a negative

reference pin. This pin should be directly

connected to the GND rail of PCB (Printed Circuit

Board). To get minimum parasitic inductance, the

path length should keep as short as possible. In

addition, the power pin (pin 5) of AZC199-04C is

a positive reference pin. This pin should directly

connect to the VDD rail of PCB., then the VDD

rail also can be protected by the power-rail ESD

clamped circuit (not shown) of AZC199-04C.

AZC199-04C can provide protection for 4 I/O

signal lines simultaneously. If the number of I/O

signal lines is less than 4, the unused I/O pins

can be simply left as NC pins.

In some cases, systems are not allowed to

be reset or restart after the ESD stress directly

applying at the I/O-port connector. Under this

situation, in order to enhance the sustainable

ESD Level, a 0.1

µF chip capacitor can be added

between the VDD and GND rails. The place of

this chip capacitor should be as close as possible

to the AZC199-04C.

In some cases, there isn’t

power rail

presented on the PCB. Under this situation, the

power pin (pin 5) of AZC199-04C can be left as

floating. The protection will not be affected, only

the load capacitance of I/O pins will be slightly

increased. Fig. 3 shows the detail connection.

1

2

3

4

5

6

To

Protected

IC

To

Protected

IC

I/O 1

I/O 2

I/O 3

I/O 4

To

I/O-port

Connector

To

I/O-port

Connector

I/O 4

I/O 3

I/O 2

I/O 1

GND rail

data

line

data

line

data

line

data

line

VDD rail

*Optional

0.1

µµµµF

Chip Cap.

Fig. 2

Data lines and power rails connection of AZC199-04C.

1

2

3

4

5

6

VDD

floated

To

Protected

IC

To

Protected

IC

I/O 1

I/O 2

I/O 3

I/O 4

To

I/O-port

Connector

To

I/O-port

Connector

I/O 4

I/O 3

I/O 2

I/O 1

data

line

data

line

data

line

data

line

GND rail

Fig. 3

Data lines and power rails connection of AZC199-04C. VDD pin is left as floating when no

power rail presented on the PCB.