HS7516 datasheet(6/8 Pages) SIPEX

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SIGNAL PROCESSING EXCELLENCE

132

Figure 4. Microprocessor Interface to SP7514

CLK

74273

VREF

(+ 25V MAX)

LSB

SP7514/

7516

74273

CLK

MSB GND

LATCHES

ADDRESS DECODER

G2A

74LS138

G2B

–

200

470

400

BDSEL

A 2

A 1

A 0

VREF

VDD

I01

I02

UNIPOLAR MODE

(2-QUADRANT)

VOUT

0 TO - V REF

(1-2 - N)

R0S

SP7516/

HS3160

HS3160, small values for C

f must be used. Resis-

tor R

p can be added, this will parallel Rj decreasing

the effective resistance. If C

f is reduced the band-

widthwillbeincreasedandsettlingtimedecreased.

However a system penalty for lowering C

f is to

increase noise gain. The tradeoff is noise vs. set-

tling time. If R

p is added then a large value (1µF or

greater)non-polarizedcapacitorC

p should be added

in series with R

p to eliminate any DC drifts. If

settling time is not important, eliminate R

p and Cp,

and adjust C

f to prevent overshoot.

Output Offset

In most applications, the output of the DAC is fed

into an amplifier to convert the DAC’s current

output to voltage. A little known and not com-

monly discussed parameter is the linearity error

versus offset voltage of the output amplifier. All

CMOS DAC’s must operate into a virtual ground,

i.e., the summing junction of an op amp. Any

amplifier’s offset from the amplifier will appear as

an error at the output (which can be related to

LSB’s of error).

Most all CMOS DAC’s currently available are

implemented using an R-2R ladder network. The

formulafornonlinearityistypically0.67mV/mV

(not derived here). However the SP7516 has a

coefficient of only 0.065mV/mV

OS. This is due to

the decoding technique described earlier. CMOS

DAC applications notes (including this one) al-

ways show a potentiometer used to null out the

amplifier’s offset. If an amplifier is chosen having

‘pretrimmed’ offset it may be possible to eliminate

this component. Consider the following calcula-

tions:

Using LF441A amplifier (low power - 741 pinout)

Specified offset: 0.5mV max

Temperature coefficient of input offset: 10

µV/°C max

OS max (0°C to 70°C)

= 0.5mV + (70

µV)10

= 1.2mV

Add'l nonlinearity (max)

= 1.2mV x 0.065mV/mV

= 78

µV (1/2 LSB @ 16 Bits!)

Where: 78

µV = 1/2 LSB @ 16 Bits (10V range)

Via the above configuration, the SP7516/HS3160

can be used to divide an analog signal by digital

code (i.e. for digitally controlled gain). The trans-

fer function is given in Table 2, where the value of

each bit is 0 or 1. Division by all “0”s is undefined

and causes the op amp to saturate.

Following the decoded section of the DAC a

standard binary weighted R-2R approach is used.

This divides each of the 16 levels (or 6.25% of

F.S.) into 4096 discrete levels (the 12 LSB’s).

Output Capacitance

The SP7516/HS3160 have very low output ca-

pacitance (C

O). This is specified both with all

switches ON and all switches OFF. Output capaci-

tance varies from 50pF to 100pF over all input

codes. This low capacitance is due in part to the

decoding technique used. Smaller switches are

used with resulting less capacitance. Three impor-

tant system characteristics are affected by C

O and

∆C

O; namely digital feedthrough, settling time,

and bandwidth. The DAC output equivalent cir-

cuit can be represented as shown in Figure 1.

Digital feedthrough is the change in analog output

due to the toggling conditions on the converter

input data lines when the analog input V

REF is at

0V. The SP7516/HS3160 very low C

O and there-

fore will yield low digital feedthrough. Inputs to

the DAC can be buffered. This input latch with

microprocessor control is shown in Figure 4.

Settling time is directly affected by C

O. In Figure

1, C

O combines with Rf to add a pole to the open

loop response, reducing bandwidth and causing

excessive phase shift - which could result in

ringing and/or oscillation. A feedback capaci-

tor, C

f must be added to restore stability. Even with

f, there is still a zero-pole mismatch due to RiCO

which is code dependent. This code dependent

mismatch is minimized when C

ORi = RfCf. How-

ever C

f must now be made larger to compensate for

worst case

∆R

iCO - resulting in reduced bandwidth

and increased settling time. With the SP7516/

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