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ADN8834ACPZ-R2 Folha de dados(PDF) 7 Page - Analog Devices

Nome de Peças ADN8834ACPZ-R2
Descrição Electrónicos  Ultracompact, 1.5 A Thermoelectric Cooler (TEC) Controller
PDF  27 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADN8834ACPZ-R2 Folha de dados(HTML) 7 Page - Analog Devices

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Data Sheet
ADN8834
Rev. B | Page 7 of 27
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A
B
C
D
E
1
2
3
4
5
VLIM/
SD
ILIM
VREF
VDD
IN2P
IN1P
OUT2
AGND
IN2N
EN/SY
OUT1
ADN8834
TOP VIEW
(BALLS ON THE BOTTOM SIDE)
IN1N
ITEC
VTEC
SFB
SW
LDR
PGNDL
PVIN
PGNDS
PGNDS
SW
PVIN
PGNDL
LDR
2.54mm
2.54mm
0.5mm
PITCH
Figure 2. WLCSP Pin Configuration (Top View)
2
1
3
4
5
6
18
17
16
15
14
13
VREF
VDD
ILIM
VLIM/SD
OUT2
IN2N
PGNDS
SW
PVINS
PVINL
LDR
PGNDL
ADN8834
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. SOLDER TO THE ANALOG
GROUND PLANE ON THE BOARD.
Figure 3. LFCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
WLCSP
LFCSP
A1, A2
18, 19
PGNDL
Power Ground of the Linear TEC Controller.
N/A1
20
TMPGD
Temperature Good Output.
A3
21
OUT1
Output of the Error Amplifier.
A4
23
IN1P
Noninverting Input of the Error Amplifier.
A5
24
IN2P
Noninverting Input of the Compensation Amplifier.
B1, B2
17
LDR
Output of the Linear TEC Controller.
B3
22
IN1N
Inverting Input of the Error Amplifier.
B4
1
IN2N
Inverting Input of the Compensation Amplifier.
B5
3
VLIM/SD
Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin
is pulled low, the device shuts down.
C1, C2
N/A1
PVIN
Power Input for the TEC Controller.
N/A1
16
PVINL
Power Input for the Linear TEC Driver.
N/A1
15
PVINS
Power Input for the PWM TEC Driver.
C3
11
ITEC
TEC Current Output.
C4
2
OUT2
Output of the Compensation Amplifier.
C5
4
ILIM
Current Limit. This pin sets the TEC cooling and heating current limits.
D1, D2
14
SW
Switch Node Output of the PWM TEC Controller.
D3
9
VTEC
TEC Voltage Output.
D4
8
EN/SY
Enable/Synchronization. Set this pin high to enable the device. An external synchronization
clock input can be applied to this pin.
D5
5
VDD
Power for the Controller Circuits.
E1, E2
12, 13
PGNDS
Power Ground of the PWM TEC Controller.
E3
10
SFB
Feedback of the PWM TEC Controller Output.
E4
7
AGND
Signal Ground.
E5
6
VREF
2.5 V Reference Output.
N/A1
0
EPAD
Exposed Pad. Solder to the analog ground plane on the board.
1 N/A means not applicable.



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