STM32F373VC datasheet(98/137 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F373xx

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DocID022691 Rev 7

6.3.17

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 60 are preliminary values derived

from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply

voltage conditions summarized in Table 22.

Note:

It is recommended to perform a calibration after each power-up.

Table 60. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

2.4

3.6

VREF+

Positive reference voltage

2.4

VDDA

VREF-

Negative reference voltage

IDDA(ADC)(1) Current consumption from VDDA VDD = VDDA = 3.3 V

0.9

IVREF

Current on the VREF input pin

160(2)

220(2)

µA

fADC

ADC clock frequency

0.6

MHz

fS(3)

Sampling rate

0.05

MHz

fTRIG(3)

External trigger frequency

fADC = 14 MHz

823

kHz

1/fADC

VAIN

Conversion voltage range

0 (VSSA or VREF-

tied to ground)

-VREF+

RSRC(3)

Signal source impedance

See Equation 1 and

Table 61 for details

RADC(3)

Sampling switch resistance

CADC(3)

Internal sample and hold

capacitor

tCAL(3)

Calibration time

fADC = 14 MHz

5.9

µs

-83

1/fADC

tlat(3)

Injection trigger conversion

latency

fADC = 14 MHz

0.214

µs

2(4)

1/fADC

tlatr(3)

Regular trigger conversion

latency

fADC = 14 MHz

0.143

µs

2(4)

1/fADC

tS(3)

Sampling time

fADC = 14 MHz

0.107

17.1

µs

1.5

239.5

1/fADC

tSTAB(3)

Power-up time

µs

tCONV(3)

Total conversion time (including

sampling time)

fADC = 14 MHz

µs

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA

on IDD is present

2. Guaranteed by characterization results.

3. Guaranteed by design.

4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 60

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