STM32WB50CG datasheet(2/119 Pages) STMICROELECTRONICS

2 / 119 page

STM32WB50CG STM32WB30CE

2/119

DS13047 Rev 5

 Memories

– 1 MB Flash memory with sector protection

(PCROP) against R/W operations, enabling

radio stack and application

– 128 KB SRAM, including 64 KB with

hardware parity check

– 20x32-bit backup register

– Boot loader supporting USART, SPI, I2C

interfaces

– OTA (over the air) Bluetooth® Low Energy

and 802.15.4 update

– 1 Kbyte (128 double words) OTP

 Rich analog peripherals (down to 2.0 V)

– 12-bit ADC 2.13 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

 System peripherals

– Inter processor communication controller

(IPCC) for communication with Bluetooth®

Low Energy and 802.15.4

– HW semaphores for resources sharing

between CPUs

– 1x DMA controller (7x channels) supporting

ADC, SPI, I2C, USART, AES, timers

– 1x USART (ISO 7816, IrDA, SPI Master,

Modbus and Smartcard mode)

– 1x SPI 32 Mbit/s

– 1x I2C (SMBus/PMBus)

– 1x 16-bit, four channels advanced timer

– 2x 16-bit, two channels timer

– 1x 32-bit, four channels timer

– 2x 16-bit ultra-low-power timer

– 1x independent Systick

– 1x independent watchdog

– 1x window watchdog

 Security and ID

– Secure firmware installation (SFI) for

Bluetooth® Low Energy and 802.15.4 SW

stack

– 2x hardware encryption AES maximum

256-bit for the application, the Bluetooth®

Low Energy and IEEE802.15.4

– Customer key storage / key manager

services

– HW public key authority (PKA)

– Cryptographic algorithms: RSA,



Diffie-Helman, ECC over GF(p)

– True random number generator (RNG)

– Sector protection against R/W operation

(PCROP)

– CRC calculation unit

– Die information: 96-bit unique ID

– IEEE 64-bit unique ID. Possibility to derive

802.15.4 64-bit and Bluetooth® Low Energy

48-bit EUI

 Up to 30 fast I/Os, 28 of them 5 V-tolerant

 Development support

– Serial wire debug (SWD), JTAG for the

application processor

– Application cross trigger

 Package is ECOPACK2 compliant

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