IS61C64B

Rev. D

07/01/02

Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice.

ISSI

assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device

specification before relying on any published information and before placing orders for products.

FEATURES

• High-speed access time: 10, 12, and 15 ns

• Automatic power-down when chip is

deselected

• CMOS low power operation

— 450 mW (typical) operating

— 250 µW (typical) standby

• TTL compatible interface levels

• Single 5V power supply

• Fully static operation: no clock or refresh

required

• Three state outputs

• One Chip Enables (

CE) for increased speed

8K x 8 HIGH-SPEED CMOS STATIC RAM

DESCRIPTION

The

8192-word by 8-bit static RAM. It is fabricated using

performance CMOS technology. This highly reliable process

coupled with innovative circuit design techniques, yields ac-

cess times as fast as 10 ns with low power consumption.

When

CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down to

250 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using one Chip Enable

input,

CE. The active LOW Write Enable (WE) controls both

writing and reading of the memory.

The IS61C64B is packaged in the JEDEC standard 28-pin,

300-mil SOJ, and TSOP.

FUNCTIONAL BLOCK DIAGRAM

A0-A12

CE

OE

WE

256 X 256

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

July 2002