STPM10 datasheet(22/47 Pages) STMICROELECTRONICS

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Theory of operation

STPM10

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Table 8: No-load detection thresholds

LTCH

KLTCH

800

1600

3200

6400

7.8

Error detection

In addition to the no-load condition and the line frequency band, the integration of power

can also be suspended due to an error detected on the source signals. There are two kinds

of error-detection circuits involved. The first

checks all the ΣΔ signals from the analog part if

any is stacked at 1 or 0 within the 1/128 of fCLK period of observation. In case of a detected

error, the corresponding ΣΔ signal is replaced with an idle ΣΔ signal, which represents a

constant value of 0. All error and other resolved flags are treated as bits of a device status

and can be read out by means of the SPI interface. Another error condition occurs if LED

pin output signals are different from the internal signals that drive them. This can occur if

some of these pins are forced to GND or to some other imposed voltage value. In this

case, the internal status bit PIN is activated, providing the information that some hardware

problem has been detected.

7.9

Tamper detection module

The STPM10 measures the current in both live and neutral wire with a time domain

multiplexing approach on a unique sigma delta modulator. This mechanism is adopted to

implement anti-tamper function. If this function is selected (see Table 7: "Configuration of

current sensors"), the live and neutral wire currents are monitored; when the difference

between the two measurements exceeds a rated threshold, the STPM10 enters the

"tamper state", while in "normal state" the two measurements are below the threshold. In

particular, both channels are not observed all the time, rather a time multiplex mechanism

is used. During the observation time of each channel, its active energy is calculated. A

tamper condition occurs when the absolute value of the difference between the two active

energy values is greater than a certain percentage of the averaged energy during the

activated tamper module (see equation below). This percentage value can be selected

between two different values (12.5% and 6.25%) according to the value of the configuration

bit CRIT. The tamper condition is detected when the following formula is satisfied:

Equation 1:

EnergyCH1 - EnergyCH2 > KCRIT (EnergyCH1 + EnergyCH2)/2

where KCRIT can be 12.5% or 6.25%.

The detection threshold is much higher than the accuracy difference of the current

channels, which should be less than 0.2 %, but, some headrooms should be left for

possible transition effect, due to accidental synchronism of actual load current change with

the rhythm of taking the energy samples. The tamper circuit works if the energies

associated with the two current channels are both positive or negative, if the two energies

have different sign, the tamper is on all the time however, the channel with the associated

higher power is selected for the final computation of energy. When internal signals are not

good enough to perform the calculations, i.e. line period is out or range or ΔΣ signals from

analog section are stacked at high or low logic level, or no-load condition is activated, the

tamper module is disabled and its state is preset to normal.

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