AD9540PCB datasheet(18/32 Pages) AD

Nome de Peças	AD9540PCB

Descrição Electrónicos	655 MHz Low Jitter Clock Generator

PDF	32 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

Logo

18 / 32 page

AD9540

Rev. 0 | Page 18 of 32

TYPICAL APPLICATION CIRCUITS

25MHz

CRYSTAL

÷M

÷R

÷N

REFIN

CHARGE

PUMP

PHASE

DETECTOR

400MHz

AD9540

CLOCK1

CLOCK1'

CML

DRIVER

DDS

DAC

VCO

CLK2

Figure 32. Dual Clock Configuration

EXTERNAL

REFERENCE

÷M

÷N

REFIN

CHARGE

PUMP

PHASE

DETECTOR

622MHz

AD9540

CLOCK1

CLOCK2

CML

DRIVER

DDS

DAC

VCO

CLK2

÷R

Figure 33. Optical Networking Clock

APPLICATION CIRCUIT DESCRIPTIONS

Dual Clock Configuration: AD9540 Configured in a

Dual-Clock Configuration

In this loop, M = 1, N = 16, and R = 4. The DDS tuning word is

also equals to ¼, so that the frequency of CLOCK 1’ equals the

frequency of CLOCK 1. Phase adjustments in the DDS provide

14-bit programmable rising edge delay capability of CLOCK 1’

with respect to CLOCK 1 (see Figure 32).

Optical Networking Clock: AD9540 Configured as an

Optical Networking Clock

The loop can be used to generate a 622 MHz clock for OC12.

The DDS can be programmed to output 8 kHz to serve as a base

reference for other circuits in the subsystem (see Figure 33).

AD9540PCB Folha de dados(PDF) 18 Page - Analog Devices

AD9540PCB Folha de dados(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Folha de dados Download

Ligação URL