LTM4664 datasheet(24/138 Pages) AD

24 / 138 page

LTM4664A

Rev. 0

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VOSNS–_C1 (N6): Channel 1 Negative Differential. Voltage

Sense Input. See VOSNS+_C1.

VOSNS+_C1 (P6): Channel 1 Positive Differential Voltage

Sense Input. Together, VOSNS+_C1 and VOSNS–_C1 serve

to kelvin sense the VOUTC1 output voltage at VOUTC1’s point

of load (POL) and provide the differential feedback signal

directly to Channel 1’s feedback loop. Command VOUTC1’s

target regulation voltage by serial bus. Its initial command

value at VINS3 power-up is dictated by NVM (non-volatile

memory) contents (factory default: 1.000V)—or, option-

ally, may be set by configuration resistors; see VOUTC1_

CFG and the 4:1 Divider Application Information section.

IN– (P10): Negative Current Sense Amplifier Input. If

the input current sense amplifier is not used, this pin

must be shorted to the IN+ and VIN3 pins. See 4:1 Divider

Application Information section for detail about the input

current sensing.

COMP_0a/COMP_1a (P11/M6): Loop Compensation

Nodes. The internal PWM loop compensation resistors

RCOMPn of the LTM4664A can be adjusted using bit

[4:0] of the MFR_PWM_COMP command. The transcon-

ductance of the LTM4664A PWM error amplifier can be

adjusted using bit [7:5] of the MFR_PWM_COMP com-

mand. These two loop compensation parameters can be

programmed when device is in operation. Refer to the

Programmable Loop Compensation subsection in the 4:1

Divider Application Information section for further details.

See MFR_PWM_COMP section.

VOSNS–_C0: (P12): Channel 0 Negative Differential Voltage

Sense Input. See VOSNS+_C0.

GL_C0, GL_C1 (P16, P5): Bottom MOSFET gate drive

in the Channel 0 power stage, Channel 1 power stage.

Utilized for debugging or monitoring purposes.

INTVCC (R7): Internal Regulator, 5.5V output. When oper-

ating the VINS3 from 7V ≤ VINS3 ≤ 16V, a LDO generates

INTVCC from VINS3_C1 to bias internal control circuits and

the MOSFET drivers of the dual 25A/30A power supply. An

external 2.2µF ceramic decoupling is required. INTVCC is

regulated regardless of the RUN_Cn pin state.

PIN FUNCTIONS

EXTVCC (R8): External Power Input to an Internal Switch

Connected to INTVCC. This switch closes and supplies

the IC power, bypassing the internal regulator whenever

EXTVCC is higher than 4.7V and VIN is higher than 7V.

EXTVCC also powers up VDD33 when EXTVCC is higher than

4.7V and INTVCC is lower than 3.8V. Do not exceed 6V

on this pin. Decouple this pin to PGND with a minimum

of 4.7μF low ESR tantalum or ceramic capacitor. If the

EXTVCC pin is not used to power INTVCC, the EXTVCC pin

must be tied GND. Its recommended to use this pin if a

bias is available to reduce power loss.

IN+ (R10): Positive Current Sense Amplifier Input. If the

input current sense amplifier is not used, this pin must

be shorted to the IN– and VINS3 pins. See 4:1 Divider

Application Information section for detail about the input

current sensing.

PGOOD_C0/PGOOD_C1 (R11/N5): Power Good Indicator

Outputs. Open-drain logic output that is pulled to ground

when the output exceeds the UV and OV regulation win-

dow. The output is deglitched by an internal 100μs filter.

A pull-up resistor to 3.3V is required in the application.

VOSNS+_C0: (R12) Channel 0 Positive Differential Voltage

Sense Input. Together, VOSNS+_C0 and VOSNS–_C0 serve to

kelvin-sense the VOUTC0 output voltage at VOUTC0’s point

of load (POL) and provide the differential feedback signal

directly to Channel 0’s feedback loop. Command VOUTC0’s

target regulation voltage by serial bus. Its initial command

value at VINS3 power-up is dictated by NVM (non-volatile

memory) contents (factory default: 1.000V)—or, option-

ally, may be set by configuration resistors; see VOUTC0_

CFG and the 4:1 Divider Application Information section.

SWC0, SWC1 (T10-T13), (T4-T7): Switching Node of

Channel 0 and Channel 1. Used for test purposes or

EMI snubbing.

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