PFD1K datasheet(10/19 Pages) MICROSEMI

10 / 19 page

10 of 19

SMD-00191 Rev D

Subject to Change Without Notice

PFD1K

Port Name

Description

Notes

REFP

Reference RF input, positive terminal

CML signal levels

REFN

Reference RF input, negative terminal

CML signal levels

VCOP

VCO RF input, positive terminal

CML signal levels

VCON

VCO RF input, negative terminal

CML signal levels

UPP

Up Charge Pump output, positive terminal

CML output level set by charge pump gain

UPN

Up Charge Pump output, negative terminal

CML output level set by charge pump gain

DNP

Down Charge Pump output, positive terminal

CML output level set by charge pump gain

DNN

Down Charge Pump output, negative terminal

CML output level set by charge pump gain

DRO

Divided Reference Output ( single ended )

CML output level, requires DC pullup

DVO

Divided VCO Output ( single ended )

CML output level, requires DC pullup

Table 2: RF Pin Description

Port Name

Description

Notes

POL

Polarity of Phase Detector

3.3 V CMOS levels, defaults to logic 0 if open

R[6:0]

Reference Prescaler Divide Ratio

3.3 V CMOS levels, defaults to logic 0 if open

V[6:0]

VCO Prescaler Divide Ratio

3.3 V CMOS levels, defaults to logic 0 if open

A[3:0]

Charge Pump Gain Control

3.3 V CMOS levels, defaults to logic 0 if open

VADJ

Charge Pump Gain Analog Control

From VEE to VCC , VCC for max output

VADR

Divided Reference Output Level Control

From VEE to VCC , VCC for max output

VADV

Divided VCO Output Level Control

From VEE to VCC , VCC for max output

VCC1-4

Positive power supply

+3.3 V @ 500 mA

VEE1-4

Negative power supply

Ground

Table 3: DC Pin Descriptions

PFD1K Folha de dados(PDF) 10 Page - Microsemi Corporation

PFD1K Folha de dados(HTML) 10 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Folha de dados Download

Ligação URL