ADP2311ACPZ-3-R7 datasheet(13/20 Pages) AD

13 / 20 page

Data Sheet

ADP2311

Rev. B | Page 13 of 20

THEORY OF OPERATION

The ADP2311 is a fully integrated, dual output, step-down dc-to-dc

regulator. The ADP2311 can operate with an input voltage from

4.5 V to 18 V and can regulate the output voltage down to 0.6 V.

The ADP2311 also integrates power-up and power-down sequence

circuitry and a watchdog timer to enhance system reliability.

CONTROL SCHEME

The ADP2311 features a fixed frequency, current mode pulse-

width modulation (PWM) control architecture. At the start of

each oscillator cycle, the high-side MOSFET turns on, placing a

positive voltage across the inductor. The inductor current increases

until the current sense signal crosses the peak inductor current

threshold, which turns off the high-side MOSFET and turns on

the low-side MOSFET. This places a negative voltage across the

inductor, reducing the inductor current. The low-side MOSFET

stays on for the remainder of the cycle.

PRECISION ENABLE/SHUTDOWN

The ADP2311 has a precision enable pin for both channels.

The EN pin has an internal pull-down current source of 5 µA

that provides a default turn-off when the EN pin is open.

When the voltage on the EN pin exceeds 1.2 V typical, Channel 1

and Channel 2 are enabled, and the internal pull-down current

source at the EN pin is reduced to 1 µA, which allows the user to

program the input voltage UVLO.

When the voltage on the EN pin falls below 1.1 V typical,

Channel 1, Channel 2, and all internal circuits are turned off,

and the device enters shutdown mode.

INTERNAL REGULATOR (VREG)

The internal regulator provides a stable voltage supply for the

internal control circuits and bias voltage for the low-side gate

drivers. It is recommended that a 1 µF ceramic capacitor be

placed between VREG and GND. The internal regulator also

includes a current-limit circuit for protection.

The PVIN1 pin provides the power supply for the internal

regulator shared by both channels.

BOOTSTRAP CIRCUITRY

The ADP2311 integrates boot regulators to provide the gate drive

voltage for the high-side MOSFETs. The regulators generate 5 V

bootstrap voltages between the BSTx pin and the SWx pin.

It is recommended that an X7R or X5R, 0.1 µF ceramic capacitor

be placed between the BSTx and the SWx pins.

SOFT START

The ADP2311 has integrated soft start circuitry to limit the

output voltage rise time and to reduce inrush current at startup.

The soft start time is fixed at 512 clock cycles (1.7 ms).

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP2311 has a peak current-limit protection circuit to

prevent current runaway. The high-side MOSFET peak current

is limited to 2 A typical. When the peak inductor current reaches

the current-limit threshold, the high-side MOSFET turns off,

the low-side MOSFET turns on, and the overcurrent counter

increments.

When the low-side MOSFET is turned on, the internal circuit

continues to monitor the current going through the low-side

MOSFET. At the end of every clock cycle, if the low-side MOSFET

source current is greater than the low-side source current limit

threshold (2.6 A typical), the high-side MOSFET stays off, the

low-side MOSFET stays on for the next cycle, and the over-

current counter increments. The high-side MOSFET turns on

again when the low-side source current is below the low-side

source current limit at the start of a cycle.

If the high-side MOSFET peak current does not exceed the peak

current limit in one cycle, the overcurrent counter is reset. If the

overcurrent counter reaches 10, the device enters hiccup mode.

During hiccup mode, the high-side and low-side MOSFETs are

both turned off. The device remains in hiccup mode for 4096

clock cycles and then attempts a soft start. If the current-limit

fault is cleared, the device resumes normal operation; if the

current-limit fault is still active, the device reenters hiccup mode.

The low-side MOSFET can also sink current from the load. If

the low-side sink current limit is exceeded, both the low-side and

high-side MOSFETs are turned off until the next cycle starts.

POWER-ON RESET (POR)

The POR pin is an active high, open-drain output that requires

a resistor to pull it up to a voltage.

The POR threshold is referenced to the FBx pin voltage (VFB)

and is specified as a percentage of VFB. The POR falling threshold

is 95% typical, 93.5% minimum, and 96.5% maximum, which

covers the full temperature range. Therefore, the typical POR

falling threshold is 95% of the typical VFB value, the minimum

POR falling threshold is 93.5% of the minimum VFB value, and

the maximum POR falling threshold is 96.5% of the maximum

VFB value.

If VFB is at the minimum value of 0.591 V, the minimum voltage

of the POR falling threshold is 0.591 V × 93.5% = 0.553 V.

If VFB is at the maximum value of 0.609 V, the maximum voltage

of the POR falling threshold is 0.609 V × 96.5% = 0.588 V.

Therefore, the worst-case POR falling threshold voltage range is

0.553 V to 0.588 V.

The typical POR falling threshold voltage is 0.6 V × 95% = 0.57 V.

ADP2311ACPZ-3-R7 Folha de dados(PDF) 13 Page - Analog Devices

ADP2311ACPZ-3-R7 Folha de dados(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Folha de dados Download

Ligação URL