Data Sheet

ADP2311

Rev. B | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

VREG

POR

TIMER

PFO

PGND1

NOTES

1. SOLDER THE EXPOSED PAD TO AN

EXTERNAL GND PLANE.

PFI

2

1

3

4

5

6

18

17

16

15

14

13

ADP2311

TOP VIEW

PGND1

BST1

BST2

PGND2

PGND2

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

Analog Ground. Connect this pin to the ground plane.

2

VREG

Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 µF ceramic

capacitor between VREG and GND.

3

TIMER

POR Sequence Selection and Delay Time Setting. This pin is used to set the POR sequence and delay time (see

the TIMER Pin Configuration section).

4

PFI

Power Fail Comparator Input. Connect an external resistor divider from PVIN2 to PFI to monitor the input voltage.

When the PFI voltage falls below the threshold voltage, the PFO pin is pulled low.

5

PFO

Power Fail Output (Open Drain).

6

POR

Power-On Reset Output (Open Drain).

7

FB2

Feedback Voltage Sense Input for Channel 2. Connect this pin to a resistor divider from the Channel 2 output

8

RSTO

Watchdog Output (Open Drain). The RSTO pin goes low if the internal watchdog timer times out because of

inactivity on the WDI input.

9

WDI

Watchdog Input. If WDI remains high or low for longer than the watchdog timeout period, the watchdog output,

RSTO, goes low. The timer is reset with each transition at the WDI input; a high to low or low to high transition

clears the counter.

10

PVIN2

Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor between

this pin and PGND2.

11, 12

SW2

Switch Node for Channel 2.

13, 14

PGND2

Power Ground for Channel 2.

15

BST2

Supply Rail for the Gate Drive of Channel 2. Place a 0.1 µF capacitor between SW2 and BST2.

16

BST1

Supply Rail for the Gate Drive of Channel 1. Place a 0.1 µF capacitor between SW1 and BST1.

17, 18

PGND1

Power Ground for Channel 1.

19, 20

SW1

Switch Node for Channel 1.

21

PVIN1

Power Input for Channel 1. Connect PVIN1 to the input power source, and connect a bypass capacitor between

this pin and PGND1.

22

EN

Precision Enable Input. An external resistor divider can be used to set the turn-on threshold. If the enable pin is

not used, connect EN to PVINx.

23

VM2

Voltage Monitor Comparator Input. Connect an external resistor divider from PVIN2 to VM2 to monitor the

input voltage. During the power-down sequence, Channel 2 turns off when the VM2 voltage falls below the

threshold voltage.

24

FB1

Feedback Voltage Sense Input for Channel 1. Connect this pin to a resistor divider from the Channel 1 output

EP

Exposed Pad. Solder the exposed pad to an external GND plane.