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SH7041A Folha de dados(PDF) 90 Page - Renesas Technology Corp

Nome de Peças SH7041A
Descrição Electrónicos  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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52
2.3.2
Addressing Modes
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8
Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Addresses Calculation
Equation
Direct register
addressing
Rn
The effective address is register Rn. (The operand
is the contents of register Rn.)
—
Indirect register
addressing
@Rn
The effective address is the content of register Rn.
Rn
Rn
Rn
Post-increment
indirect register
addressing
@Rn+
The effective address is the content of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
Rn
Rn
1/2/4
+
Rn + 1/2/4
Rn
(After the
instruction
executes)
Byte: Rn + 1
→ Rn
Word: Rn + 2
→ Rn
Longword:
Rn + 4
→ Rn
Pre-decrement
indirect register
addressing
@–Rn
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
1/2/4
Rn – 1/2/4
–
Rn – 1/2/4
Byte: Rn – 1
→ Rn
Word: Rn – 2
→ Rn
Longword:
Rn – 4
→ Rn
(Instruction
executed with
Rn after
calculation)



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