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SH7041A Folha de dados(PDF) 446 Page - Renesas Technology Corp

Nome de Peças SH7041A
Descrição Electrónicos  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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12.7.17
Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set .
Figure 12.94 shows the operation timing in this case.
φ
Address
Write signal
TCNT input
clock
TCNT
TCFV flag
H'FFFF
N
TCNT write data
Disabled
TCNT write cycle
T1
T2
TCNT address
Figure 12.94 Contention between TCNT Write and Overflow



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