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SH7041A Folha de dados(PDF) 384 Page - Renesas Technology Corp

Nome de Peças SH7041A
Descrição Electrónicos  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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SH7041A Folha de dados(HTML) 384 Page - Renesas Technology Corp

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Phase Count Mode 4: Figure 12.33 shows an example of phase counting mode 4 operation. Table
12.12 lists the up counting and down counting conditions for the TCNT.
Increment
Decrement
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
TCNT value
Time
Figure 12.33 Phase Counting Mode 4 Operation
Table 12.12 Phase Count Mode 4 Up/Down Counting Conditions
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
1 (high level)
Rising edge
Increment
0 (low level)
Falling edge
Rising edge
0 (low level)
Does not count (don’t care)
Falling edge
1 (high level)
1 (high level)
Falling edge
Decrement
0 (low level)
Rising edge
Rising edge
1 (high level)
Does not count (don’t care)
Falling edge
0 (low level)
Phase Counting Mode Application Example: Figure 12.34 shows an example where channel 1
is set to phase counting mode and is teamed with channel 0 to input a two-phase encoder pulse for
a servo motor to accurately detect position and speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A phase and B phase are input to
the TCLKA and TCLKB pins.
Channel 0 is set so that the TCNT counter is cleared on a TGR0C register compare-match, and the
TGR0A and TGR0C registers are used with the compare-match function to establish the speed
control and position control periods. The TGR0B register is used with the input capture function,
and the TGR0B and TGR0D registers are employed for buffer operation. The channel 1 counter



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