SST26VF040A-80ISLASHSNVAO datasheet(12/73 Pages) MICROCHIP

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DS20006292B-page 12

SST26VF040A

4.7.4

WRITE SUSPEND ERASE STATUS

(WSE)

The Write Suspend Erase status (WSE) indicates when

an erase operation is suspended. The WSE bit is ‘1’

after the host issues a suspend command during an

erase operation. Once the suspended erase resumes,

the WSE bit is reset to ‘0’.

4.7.5

WRITE SUSPEND PROGRAM

STATUS (WSP)

The Write Suspend Program status (WSP) bit indicates

when a program operation is suspended. The WSP

is ‘1’ after the host issues a suspend command during

the program operation. Once the suspended program

operation resumes, the WSP bit is reset to ‘0’.

4.7.6

RESET/HOLD ENABLE (RSTHLD)

The Reset/Hold Enable (RSTHLD) bit is a nonvolatile

bit that configures the RST#/HOLD#/SIO3 pin to be

either the RST# pin or the Hold# pin when not config-

ured as an I/O. There is latency associated with writing

to the RSTHLD bit. Poll the BUSY bit in the STATUS

internal, self-timed write operation.

4.7.7

WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that enables the WP# pin. The Write-Protect (WP#)

pin and the Write-Protect Enable (WPEN) bit control

the programmable hardware write-protect feature.

Setting the WP# pin to low, and the WPEN bit to ‘1’,

enables hardware write protection. To disable

hardware write protection, set either the WP# pin to

high or the WPEN bit to ‘0’. There is latency associated

with writing to the WPEN bit. Poll the BUSY bit in the

STATUS register or wait TCONFIG for the completion

of the internal, self-timed write operation. When the

chip is hardware write-protected, only write operations

to the BPL bit in the STATUS register and Configuration

Write Protection” and Table 4-1 for more information

about the functionality of the WPEN bit.

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