HCS08 datasheet(175/316 Pages) NXP

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Inter-Integrated Circuit (S08IICV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

175

After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first

byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them

are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does

not match.

After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC

interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this

interrupt.

11.4.3

General Call Address

General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches

the general call address as well as its own slave address. When the IIC responds to a general call, it acts as

a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after

the first byte transfer to determine whether the address matches is its own slave address or a general call.

If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied

from a general call address by not issuing an acknowledgement.

11.5

Resets

The IIC is disabled after reset. The IIC cannot cause an MCU reset.

11.6

Interrupts

The IIC generates a single interrupt.

An interrupt from the IIC is generated when any of the events in Table 11-12 occur, provided the IICIE bit

is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC

control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You

can determine the interrupt type by reading the status register.

11.6.1

Byte Transfer Interrupt

The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion

of byte transfer.

Slave Address

1st 7 bits

R/W

Slave Address

2nd byte

Slave Address

1st 7 bits

R/W

Data

...

Data

11110 + AD10 + AD9

AD[8:1]

11110 + AD10 + AD9

Table 11-11. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address

Table 11-12. Interrupt Summary

Interrupt Source

Status

Flag

Local Enable

Complete 1-byte transfer

TCF

IICIF

IICIE

Match of received calling address

IAAS

IICIF

IICIE

Arbitration Lost

ARBL

IICIF

IICIE

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