HCS08 datasheet(169/316 Pages) NXP

169 / 316 page

Inter-Integrated Circuit (S08IICV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

169

11.3.5

IIC Data I/O Register (IICD)

Table 11-7. IICS Field Descriptions

Field

Description

TCF

Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or

immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the

IICD register in receive mode or writing to the IICD in transmit mode.

0 Transfer in progress

1 Transfer complete

IAAS

Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address or

when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit.

0 Not addressed

1 Addressed as a slave

BUSY

Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set

when a start signal is detected and cleared when a stop signal is detected.

0 Bus is idle

1Bus is busy

ARBL

Arbitration Lost. This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared

by software by writing a 1 to it.

0 Standard bus operation

1 Loss of arbitration

SRW

Slave Read/Write. When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the

calling address sent to the master.

0 Slave receive, master writing to slave

1 Slave transmit, master reading from slave

IICIF

IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by

writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:

•

One byte transfer completes

•

Match of slave address to calling address

•

Arbitration lost

0 No interrupt pending

1 Interrupt pending

RXAK

Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after

the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge

signal is detected.

0 Acknowledge received

1 No acknowledge received

321

DATA

Reset

000

Figure 11-7. IIC Data I/O Register (IICD)

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