ADC3641 datasheet(23/77 Pages) TI

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8.3.1.2 Analog Front End Design

The ADC364x is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch

from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low

output impedance, a termination network may be needed. Additionally a passive DC bias circuit is required in

AC-coupled applications which can be combined with the termination network.

8.3.1.2.1 Sampling Glitch Filter Design

The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter

performance is dependent on input frequency and therefore the following filter designs are recommended for

different input frequency ranges as shown in Figure 8-4 and Figure 8-5 (assuming 50 Ω source impedance).

100 pF

180nH

Termination

Figure 8-4. Sampling glitch filter example for input frequencies from DC to 30 MHz

Termination

82 pF

120nH

100pF

120nH

100pF

150nH

Figure 8-5. Sampling glitch filter example for input frequencies from 30 to 70 MHz

8.3.1.2.2 Single Ended Input

The ADC can be configured to operate with single ended input instead of differential using just the positive signal

input. This operating mode must be enabled via SPI register write (address 0x11). The single ended signal is

connected to the negative ADC input and both the positive and negative input need to be biased to VCM as

shown in Figure 8-6.

INM

INP

INM

0.56V

-0.56V

0.56V

-0.56V

INP

Figure 8-6. Single ended analog input: AC coupled (left) and DC coupled (right)

The signal swing is now reduced by 6-dB (single ended input with 1.125 Vpp vs differential 2.25 Vpp), and the

resulting SNR is reduced by 3-dB.

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ADC3643

SBAS886 – OCTOBER 2020

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