ICS2402 datasheet(1/7 Pages) ICST

Nome de Peças	ICS2402

Descrição Electrónicos	Multiplier and Zero Delay Buffer

PDF	7 Pages

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Fabricante Electrônico	ICST [Integrated Circuit Systems]

Página de início	http://www.icst.com

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ICS2402

MDS 2402 D

1

Revision 122104

Integrated Circuit Systems, Inc.

● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

Multiplier and Zero Delay Buffer

Description

The ICS2402 is a high-performance Zero Delay Buffer

(ZDB) which integrates ICS’ proprietary analog/digital

Phase-Locked Loop (PLL) techniques. The chip is part

of ICS’ ClockBlocksTM family and was designed as a

performance upgrade to meet today’s higher speed and

lower voltage requirements. The zero delay feature

means that the rising edge of the input clock aligns with

the rising edges of both output clocks, giving the

appearance of no delay through the device.

The ICS2402 is ideal for synchronizing outputs in a

large variety of systems, from personal computers to

data communications to graphics/video. By allowing

off-chip feedback paths, the device can eliminate the

delay through other devices.

Features

• 8-pin SOIC package

• Available in Pb (lead) free package

• Absolute jitter ±100 ps

• Propagation Delay of ±600 ps

• Output multiplier of 2X

• Output clock frequency up to 80 MHz

• Can recover degraded input clock duty cycle

• Output clock duty cycle of 45/55

• Full CMOS clock swings with 25 mA drive capability

at TTL levels

• Advanced, low power CMOS process

• Operating voltage of 3.3 V or 5 V

Block Diagram

Phase

Detector,

Charge

Pump,

and

Loop

Filter

divide

by N

CLK1

ICLK

FBIN

S0

VCO

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