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TBD Folha de dados(PDF) 8 Page - Integrated Circuit Systems |
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TBD Folha de dados(HTML) 8 Page - Integrated Circuit Systems |
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8 / 11 page ![]() 843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006 8 Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. To calculate worst case power dissipation into the load, use the following equations which assume a 50 Ω load, and a termination voltage of V CC - 2V. • For logic high, V OUT = V OH_MAX = V CC_MAX – 0.9V (V CCO_MAX - V OH_MAX ) = 0.9V • For logic low, V OUT = V OL_MAX = V CC_MAX – 1.7V (V CCO_MAX - V OL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R L ] * (V CC_MAX - V OH_MAX ) = [(2V - (V CC_MAX - V OH_MAX ))/R L ] * (V CC_MAX - V OH_MAX ) = [(2V - 0.9V)/50 Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R L ] * (V CC_MAX - V OL_MAX ) = [(2V - (V CC_MAX - V OL_MAX ))/R L ] * (V CC_MAX - V OL_MAX ) = [(2V - 1.7V)/50 Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION Q1 V OUT V CC RL 50 V CC - 2V |
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