ICS601-02

Low Phase Noise Clock Multiplier

MDS 601-02 D

4

Revision 111204

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (note 1)

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature, I version

Industrial temperature

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)

DC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)

DC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)

Operating Voltage, VDD

3.0

5.5

V

Output Buffer Voltage, VDDP

2.375

VDD

V

Input High Voltage, VIH, X1/ICLK pin only

Note 3

(VDD/2)+1

V

Input Low Voltage, VIL, X1/ICLK pin only

Note 3

(VDD/2)-1

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Output High Voltage, VOH, CMOS level

IOH=-4mA

VDD-0.4

V

Output High Voltage, VOH

IOH=-12mA

2.4

V

Output Low Voltage, VOL

IOL=12mA

0.4

V

Operating Supply Current, IDD

No Load, 125 MHz

9

20

mA

Short Circuit Current

Each output

±40

±60

mA

Input Capacitance

OE, select pins

5

pF

AC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)

AC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)

AC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted)

Input Frequency

10

27

MHz

Output Frequency

at 3.3V or 5V

170

MHz

Output Clock Rise Time

0.8 to 2.0V, no load

1.5

ns

Output Clock Fall Time

0.8 to 2.0V, no load

1.5

ns

Output Clock Duty Cycle

At VDD/2

45

50

55

%

Maximum Absolute Jitter, short term, 125 MHz No load

±50

±75

ps

Maximum Jitter, one sigma, 125 MHz (x5)

No load

18

25

ps

Phase Noise, relative to carrier, 125 MHz (x5)

100 Hz offset

-108

dBc/Hz

Phase Noise, relative to carrier, 125 MHz (x5)

1 kHz offset

-123

dBc/Hz

Phase Noise, relative to carrier, 125 MHz (x5)

10 kHz offset

-132

dBc/Hz

Phase Noise, relative to carrier, 125 MHz (x5)

100 kHz offset

-125

dBc/Hz

Electrical Specifications

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the

device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may

affect device reliability.

2. The phase relationship between input and output can change at power up. For a fixed phase

relationship, see the ICS570 or ICS670.

3. Switching occurs nominally at VDD/2.