EM6812F2TP24B datasheet(23/81 Pages) EMMICRO

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EM6812

www.emmicroelectronic.com

Clock management

8.1

Basic features

The EM6812 core and peripherals use several clock sources that can be involved in the same time. There are two main

clock domains and both of them are split in two sub-sources:

•

High frequency clock sources

- RC oscillator 1MHz or 10MHz base frequency

- External clock input from PA[4] or PA[5]

•

Low frequency clock source

- 32kHz Crystal oscillator (typical watch crystal)

- External clock input on terminal CLKOUT instead of crystal

The main features of the clock management system are:

•

In high frequency domain

Fully internal RC oscillator.

No external component needed.

Trimmable, continuous RC based frequencies from typically 75kHz up to 14MHz.

Pre-Division factors for CPU and Peripheral clocks of 1, 2, 4 or 8 are available.

Accurate frequency generation due to software FLL using RC trim and known timing.

Automatic clock selection ( ~32kHz ) on Prescaler1 if the Xtal is not available.

Power saving switch in case of RC Oscillator is not used (i.e. CPU in Halt).

•

In low frequency domain

Lowest power watch type Crystal oscillator on 32kHz.

RTC signal generation, division on Prescaler1.

3 fix interval interrupts to the CPU.

•

In both frequency domains

High and low frequency clock domains are fully synchronized for working together.

CPU can read registers on the fly thanks to the synchronization between both frequency domains.

Completely free of clock glitches, even when switching clocks while running.

Fully synchronous core operations.

Two clock prescalers (dividers) for the peripheral clock generation

Independent clock selection for both prescalers (high or low frequency domain).

8.1.1

Overview

Figure 15. Clock management block diagram

Note:

When both frequency domains are used, the minimum frequency after pre-division (F2) should be at least 8 times higher than

the maximum low frequency (F1) to allow for proper system synchronization.

PA[4]

PA[5]

ExtHFck

SelExtLFck

Xtal

OSCOUT

EnRc

EnXtal

Pre-Divider

1/ /2 /4 /8

F 2

CPU

Peripheral

clock selection

Clock

synchronization

F2 > 8*F1

CkPeri_Low_Freq

CkCPU

CkPeri_High_Freq

CoolRISC

CPU

Halt

Prescaler1

Prescaler2

Pr2Ck[9:0]

Pr1Ck[15:0]

Int0[3:1]

(128Hz, 32Hz, 1Hz)

SelExtHFck

ExtLFck

LFck

HFck

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