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ICS1562B Folha de dados(PDF) 10 Page - Integrated Circuit Systems |
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ICS1562B Folha de dados(HTML) 10 Page - Integrated Circuit Systems |
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10 / 20 page ![]() REG# BIT(S) BIT REF. DESCRIPTION 11 0-1 S[0]..S[1] PLL post-scaler/test mode select bits S[1] S[0] DESCRIPTION 0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider drives the LOAD output which, in turn, drives the N2 divider. 1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD output which, in turn, drives the N2 divider. 11 2 AUX_CLK When in the AUXEN clock mode, this bit controls the differential outputs. 11 3 AUX_N1 When in the AUXEN clock mode, this bit controls the LOAD output (and consequently the N2 output according to its programming). When not in the AUXEN clock mode, this bit, if set to one, will over- ride the N1 divider modulus and output the VCO frequency divided by two [F(PLL)/2] at the LOAD output. 12 0 RESERVED Must be set to zero. 12 1 JAMPLL Tristates phase detector outputs; resets phase detector logic, and resets R, A, M, and N2 counters. 12 2 DACRST Set to zero for normal operation. When set to one, the CLK+output is kept high and the CLK- output is kept low. (All other device func- tions are unaffected.) When returned to zero, the CLK+ and CLK- outputs will resume toggling on a rising edge of the LD output (+/- 1 CLK period). To initiate a RAMDAC reset sequence, simply write a one to this register bit followed by a zero. 12 3 SELXTAL When set to logic 1, passes the reference frequency to the post-scaler. 15 0 ALTLOOP Controls substitution of N1 and N2 dividers into feedback loop of PLL. When this bit is a logic 1, the N1 and N2 dividers are used. 15 3 PDRSTEN Phase-detector reset enable control bit. When this bit is set, the AD3 pin becomes a transparent reset input to the phase detector. See "Internal Feedback Operation" section for more details on the operation of this function. ICS1562B 10 |
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