ICS252MPLF datasheet(1/9 Pages) ICST

Nome de Peças	ICS252MPLF

Descrição Electrónicos	Field Programmable Dual Output SS VersaClock Synthesizer

PDF	9 Pages

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Fabricante Electrônico	ICST [Integrated Circuit Systems]

Página de início	http://www.icst.com

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ICS252

MDS 252 B

1

Revision 011606

Integrated Circuit Systems, Inc.

● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

Field Programmable Dual Output SS VersaClock Synthesizer

Description

The ICS252 is a low cost, dual-output, field

programmable clock synthesizer. The ICS252 can

generate two output frequencies from 314 kHz to 200

MHz using up to two independently configurable PLLs.

The outputs may employ Spread Spectrum techniques

to reduce system electro-magnetic interference (EMI).

Using ICS’ VersaClock™software to configure the PLL

and output, the ICS252 contains a One-Time

Programmable (OTP) ROM to allow field

programmability. Programming features include 4

selectable configuration registers.

The device employs Phase-Locked Loop (PLL)

techniques to run from a standard fundamental mode,

inexpensive crystal, or clock. It can replace multiple

crystals and oscillators, saving board space and cost.

The device also has a power-down feature that

tri-states the clock outputs and turns off the PLLs when

the PDTS pin is taken low.

The ICS252 is also available in factory programmed

custom versions for high-volume applications.

Features

• 8-pin SOIC package

• Two addressable registers

• Input crystal frequency of 5 to 27 MHz

• Clock input frequency of 3 to 150 MHz

• Output clock frequencies up to 200 MHz

• Configurable Spread Spectrum Modulation

• Operating voltage of 3.3 V

• Replaces multiple crystals and oscillators

• Controllable output drive levels

• Advanced, low-power CMOS process

• Available in Pb (lead) free packaging

Block Diagram

Crystal

Oscillator

GND

VDD

PDTS

PLL2

Divide

Logic

and

Output

Enable

Control

SEL

CLK2

CLK1

OTP

ROM

with

PLL

Values

X2

Crystal

External capacitors

are required.

X1

PLL1

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