ICS149317 datasheet(3/11 Pages) ICST

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Clock Synthesizer for Portable Systems

MDS 1493-17 A

Revision 101005

Integr ated Circuit System s

● 525 Ra ce Stree t, Sa n Jose, CA 951 26 ● te l (4 08) 297 -1201 ● www.icst.com

ICS1493-17

PRELIMINAR Y INFORMA T ION

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the

ICS1493-17 must be isolated from system power

supply noise to perform optimally.

A decoupling capacitor of 0.01µF must be connected

between each VDD and the PCB ground plane.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50

Ω trace (a

commonly used trace impedance), place a 33

Ω resistor

in series with the clock line, as close to the clock output

pin as possible. The nominal impedance of the clock

output is 20

Ω.

I2C External Resistor Connection

The SCK and SDATA pins can be connected to any

voltage between 1.71 V and 2.625 V.

Crystal Load Capacitors

No external crystal load capacitors are required. To

save discrete component cost, the ICS1493-17

integrates on-chip capacitance to support a crystal with

CL=10 pF. It is important to keep stray capacitance to a

minimum by using very short PCB traces (and no vias)

between the crystal and device.

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) The 0.01µF decoupling capacitors should be

mounted on the component side of the board as close

to the VDD pin as possible. No vias should be used

between the decoupling capacitors and VDD pins. The

PCB trace to VDD pins should be kept as short as

possible, as should the PCB trace to the ground via.

2) The external crystal should be mounted just next to

the device with short traces. The X1 and X2 traces

should not be routed next to each other with minimum

spaces, instead they should be separated and away

from other traces.

3) To minimize EMI, the 33

Ω series termination resistor

should be placed close to the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers. Other signal traces should be routed

away from the ICS1493-17. This includes signal traces

just underneath the device, or on layers adjacent to the

ground plane layer used by the device.

VDD

Power

Connect to +1.8 V.

Output

Connect to 27 MHz crystal or float for clock input.

Input

Crystal connection. Connect to 27 MHz crystal or clock input.

Number

Name

Type

Pin Description

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