PRELIMINARY

PLL650-08

Network LAN Clock Source

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 07/15/02 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• 1 output fixed at 100MHz , 1 output fixed at 125MHz .

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTIONS

The PLL 650-08 is a low cost, low jitter, and high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, the chip

accepts 25MHz crystal, and produces multiple output

clocks for networking chips, and ASICs.

PIN CONFIGURATION

BLOCK DIAGRAM

XTAL

OSC

100MHz

XIN

XOUT

125MHz

Control

Logic

1

2

3

4

5

6

7

8

VDD

100MHz

GND

125MHz

XIN

XOUT

GND

VDD