P521-23

Low Phase Noise PECL VCXO (100MHz to 200MHz)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 [www.phaselink.com]

Rev 7/28/04 Page 2

PAD ASSIGNMENT AND DESCRIPTION

Pin #

Name

Description

1

OSCOFFSEL

Oscillator Off Selection input pad. When low, turns off the oscillator when output is disabled.

When high (default), oscillator running when output is disabled.

Internal pull-up

2

GNDOSC

GND connection for oscillator circuitry.

3

VCON

Control Voltage input. Use this pin to change the output frequency by varying the applied

Control Voltage.

4

XIN

Crystal oscillator input pin.

5

XOUT

Crystal oscillator output pin.

6

OECTRL

OE input pad. See table on page 1.

7

DNC

Do Not Connect.

8

GND

Ground connection.

9

GND

Ground connection.

10

Q

PECL Output.

11

QBAR

PECL complementary output.

12

VDDBUF

VDD connection for output buffer circuitry.

VDDBUF should be separately decoupled from other VDDs whenever possible.

13

VDDANA

VDD connection for analog circuitry.

VDDANA should be separately decoupled from other VDDs whenever possible.

14

OESEL

Selector input to choose the OE control logic. See table on page 1.

15

BUFZSEL

Output impedance selector

16

VDDOSC

VDD connection for oscillator circuitry.

VDDOSC should be separately decoupled from other VDDs whenever possible.