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AT24CSW01X Folha de dados(PDF) 29 Page - Microchip Technology |
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AT24CSW01X Folha de dados(HTML) 29 Page - Microchip Technology |
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29 / 41 page ![]() word address and data word byte indicates the Security register is not currently locked. A NACK response indicates the AT24CSW01x/AT24CS02x is already locked. Please refer to Determining the Lock State of the Security Register for details about determining the Lock status of the AT24CSW01x/AT24CS02x. The sequence completes with a Stop condition being sent to the device, which initiates a self-timed internal write cycle. The Lock operation will conclude upon completion of that write cycle, subsequently making the Security register permanently read-only. Read operations are always allowed to the device. Figure 10-3. Lock Command SCL SDA Device Address Byte Word Address Byte Data Word (”Don’t Care” bits) Start by Host ACK from Client MSb MSb Stop by Host MSb 1 2 3 4 5 6 7 8 9 1 0 1 1 # # # 0 0 1 2 3 4 5 6 7 8 9 X X X X X X X X 0 0 1 1 0 X X X X 0 1 2 3 4 5 6 7 8 9 ACK from Client ACK from Client Note: # indicates the hardware address value which is managed by the ordering code of the device (see Table 6-2). 10.3.2 Determining the Lock State of the Security Register The Lock state of the device can be determined by sending a subset of the Lock command to the device. Only the device address byte and word address byte need to be transmitted to the device to determine the Lock state. An ACK response to the word address byte indicates the Lock has not been set while a NACK response indicates the Lock has been set. If the Lock has already been set, it cannot be undone. The abbreviated Lock sequence is completed by the host sending a Stop condition to the device. Figure 10-4. Determining the Security Register Lock State SCL SDA Device Address Byte Word Address Byte Start by Host ACK from Client MSb MSb Stop by Host 1 2 3 4 5 6 7 8 9 1 0 1 1 # # # 0 0 1 2 3 4 5 6 7 8 9 0 1 1 0 X X X X 0/1 ACK from Client if Unlocked NACK from Client if Locked Note: # indicates the hardware address value which is managed by the ordering code of the device (see Table 6-2). AT24CSW01X/AT24CSW02X Security Register © 2020-2021 Microchip Technology Inc. and its subsidiaries Datasheet DS20006396B-page 29 |
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