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SOLOMON
Rev 1
.3
01/2003
SSD0817 Series
4
DIE PAD ARRANGEMENT
Figure 2 – SSD0817 Pin Assignment
Gold Bump Alignment Mark
This alignment mark contains gold
bump
for
IC
bumping
process
alignment and IC identifications. No
conductive tracks should be laid
underneath this mark to avoid short
circuit.
Note:
1. The gold bumps face up in this
diagram
2. All dimensions in µm and (0,0) is the
center of the chip
Die Size:
8.66 mm X 1.48 mm
Die Thickness: 550 +/- 25 um
Bump Pitch:
60 um [Min]
Bump Height:
Nominal 18 um
Tolerance
< 4 um within die
< 8 um within lot
PIN #1
(-3878.7, 237.475)
X
35
8.75
X
Center (-3876.1625, 323.6625)
26.25
26.25
26.25
X
Center (2751.9625, 323.6625)
26.25
26.25
26.25
Center (3875.55, 149.275)
16.8 13.65 12.6
73.5
X
8.75
(2755.725, 237.475)
35
T5
T4
VF
IIC2
VSS
IRS
VDD
C1
VSS
C0
VDD
/IIC1
TEST7
VSS
CLS
M/S
VDD
T6
VL6
VL6
VL6
VL5
VL5
VL5
VL4
VL4
VL4
VEE
VL3
VL3
VL3
VL2
VL2
VL2
VEE
C4N
C4N
C4N
C2P
C2P
C2P
C2N
C2N
C2N
VEE
C1N
C1N
C1N
C1P
C1P
C1P
C3N
C3N
C3N
T2
VEE
VEE
VEE
VEE
VEE
VEE
VSS1
VSS1
VSS1
VSS1
VSS1
VSS
VSS
VSS
T1
T0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
TEST6
TEST5
SA0
SCL
TEST4
TEST3
SDA in
SDA out
VDD
TEST2
TEST1
VSS
TEST0
VEE
VEE
/RES
VDD
CS2
/CS1
VSS
/DOF
CL
M
MSTAT
ROW10
ROW9
ROW8
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
ICONS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
254 255
1
277
276
126
125
104 103
(-3878.7, 237.475)
(2755.725, 237.475)
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