ACE25QC800GLDPTH datasheet(39/58 Pages) ACE

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ACE25QC800G

8M BIT SPI NOR FLASH

VER 1.2

Enable Reset (66H) and Reset Device (99H)

Because of the small package and the limitation on the number of pins, the ACE25QC800G provides a

software Reset instruction instead of a dedicated RESET pin. Once the software Reset instruction is

accepted, any on-going internal operations will be terminated and the device will return to its default

power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable

Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap

Bit setting (W6-W4).

To avoid accidental reset, both “Enable Reset (66h)” and “Reset (99h)” instructions must be issued in

sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will

disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to

reset the device. Once the Reset command is accepted by the device, the device will take approximately

30us to reset. During this period, no command will be accepted.

The Enable Reset (66h) and Reset (99h) instruction sequence is shown in Figure 29.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation

when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and

the SUS bit in Status Register before issuing the Reset command sequence.

Figure29. Enable Reset (66h) and Reset (99h) Command Sequence

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