MPC755EC datasheet(43/56 Pages) NXP

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

System Design Information

Figure 24. JTAG Interface Connection

HRESET

HRESET 6

From Target

Board Sources

HRESET

SRESET

VDD_SENSE

5 1

2 k

10 k

OVDD

CHKSTP_IN

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TRST

(if any)

14 2

Key

QACK

OVDD

10 k

OVDD

10 k

OVDD

10 k

QACK

CHKSTP_OUT

KEY

No Pin

COP Connector

Physical Pin Out

10 k

Ω 4

OVDD

2 k

Ω 3

Ω 5

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC755. Connect

pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP

header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect

HRESET from the target source to TRST of the part through a 0-

Ω isolation resistor.

6. The COP port and target board should be able to independently assert HRESET and TRST to the

processor in order to fully control the processor as shown above.

TRST 6

10 k

OVDD

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