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PSD813F1AV-90MIT Folha de dados(PDF) 89 Page - STMicroelectronics

Nome de Peças PSD813F1AV-90MIT
Descrição Electrónicos  Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V
PDF  110 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
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PSD813F1AV-90MIT Folha de dados(HTML) 89 Page - STMicroelectronics

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PSD813F1V
Table 55. READ Timing (5V devices)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
6. In Turbo Off mode, add 10ns to tAVQV.
Symbol
Parameter
Conditions
-90
-12
-15
Turbo
Off
Unit
MinMax
MinMax
MinMax
tLVLX
ALE or AS Pulse Width
20
22
28
ns
tAVLX
Address Setup Time
(Note 3)
6
8
10
ns
tLXAX
Address Hold Time
(Note 3)
89
11
ns
tAVQV
Address Valid to Data Valid
(Notes 3,6)
90
120
150
+ 10
ns
tSLQV
CS Valid to Data Valid
100
135
150
ns
tRLQV
RD to Data Valid 8-Bit Bus
(Note 5)
32
35
40
ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note 2)
38
42
45
ns
tRHQX
RD Data Hold Time
(Note 1)
00
0
ns
tRLRH
RD Pulse Width
(Note 1)
32
35
38
ns
tRHQZ
RD to Data High-Z
(Note 1)
25
35
38
ns
tEHEL
E Pulse Width
32
36
38
ns
tTHEH
R/W Setup Time to Enable
10
13
18
ns
tELTL
R/W Hold Time After Enable
0
0
0
ns
tAVPV
Address Input Valid to
Address Output Delay
(Note 4)
25
28
32
ns



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