ADPA7007AEHZ-R7 datasheet(21/23 Pages) AD

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Data Sheet

ADPA7007

Rev. 0 | Page 21 of 23

HMC980LP4E BIAS SEQUENCE

The dc supply sequencing in the Power-Up Sequence section

and the Power-Down Sequence section is required to prevent

damage to the HMC980LP4E when using it to control the

ADPA7007.

Power-Up Sequence

The power-up sequence is as follows:

Set VDIG (Pin 9) of both HMC980LP4E devices to 3.3 V.

Set the VDD pins of both HMC980LP4E devices to

5.765 V.

Set VNEG (Pin 15) of both HMC980LP4E devices to

−1.5 V. This step is not needed if using an internally

generated voltage.

Set EN (Pin 5) of both HMC980LP4E devices to 3.3 V

(transitioning from 0 V to 3.3 V turns on VGATE and

VDRAIN).

Power-Down Sequence

The power-down sequence is as follows:

Set EN (Pin 5 of both HMC980LP4E devices) to 0 V

(transitioning from 3.3 V to 0 V turns off VDRAIN and

VGATE).

Set VNEG (Pin 15 of both HMC980LP4E devices) to 0 V.

This step is not needed if using an internally generated

voltage.

Set the VDD pins of both HMC980LP4E devices to 0 V.

Set VDIG (Pin 9 of both HMC980LP4E devices) to 0 V.

When the HMC980LP4E bias control circuit is set up, toggle

the bias to the ADPA7007 on or off by applying 3.3 V or 0 V,

respectively, to the EN pin of the HMC980LP4E. At EN = 3.3 V,

the VGATE pin of the HMC980LP4E drops to −1.5 V and the

VDRAIN pin of the HMC980LP4E turns on at 5 V. VGATE

then rises until IDRAIN = 1800 mA, and the closed control loop

regulates IDRAIN at 1800 mA. When EN = 0 V, VGATE is set to

−1.5 V, and VDRAIN is set to 0 V (see Figure 58 and Figure 59).

CH1 2V

CH3 2V

CH2 1V

CH4 2V

M20.0ms

A CH1

1.12V

50.00%

VDD

VDRAIN

VGATE

Figure 58. Turn On HMC980LP4E Outputs to ADPA7007

CH1 2V

CH3 2V

CH2 1V

CH4 2V

M20.0ms

A CH1

1.12V

50.00%

VDD

VDRAIN

VGATE

Figure 59. Turn Off HMC980LP4E Outputs to ADPA7007

CONSTANT DRAIN CURRENT BIASING vs.

CONSTANT GATE VOLTAGE BIASING

The HMC980LP4E uses a feedback loop to continuously adjust

VGATE to maintain a constant drain current over dc supply

variation, temperature, RF input/output level, and device to

device variation. Constant drain current bias is the preferred

method for reducing time in calibration procedures and for

maintaining consistent performance over time.

In comparison to a constant gate voltage bias, where the current

increases when RF power is applied, a constant drain current has

a slightly lower output P1dB. This output P1db is shown in

Figure 63, where the RF performance is slightly lower than

constant gate bias voltage operation due to a lower drain current at

high input power (see Figure 60) as the HMC980LP4E reaches

1 dB compression.

The output P1dB performance for constant drain current bias

can be increased toward constant gate voltage bias performance

by increasing the set current toward the IDD value it reaches

under RF drive in the constant gate voltage bias condition (see

Figure 63).

The limit of increasing drain current under the constant

current operation is set by the thermal limitations found in

Table 4 with the maximum power dissipation specification. As

the IDD increase continues, the actual output P1dB does not

continue to increase indefinitely but the power dissipation

increases linearly. Therefore, take the trade-off between the

power dissipation and output P1dB performance into

consideration when using constant drain current biasing.

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