IMXRT1024IEC datasheet(22/90 Pages) NXP

22 / 90 page

i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020

NXP Semiconductors

Electrical characteristics

4.1.5

Maximum supply currents

The data shown in Table 13 represent a use case designed specifically to show the maximum current

consumption possible. All cores are running at the defined maximum frequency and are limited to L1

cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited

practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to

specifically show the worst case power consumption.

See the i.MX RT1024 Power Consumption Measurement Application Note for more details on typical

power consumption under various use case definitions.

4.1.6

Low power mode supply currents

Table 14 shows the current core consumption (not including I/O) of i.MX RT1024 processors in selected

low power modes.

Table 13. Maximum supply currents

Power Rail

Conditions

Max Current

Unit

DCDC_IN

Max power for chip at 105oC with core

mark run on FlexRAM

VDD_HIGH_IN

Include internal loading in analog

VDD_SNVS_IN

—

250

A

USB_OTG1_VBUS

25 mA for each active USB interface

VDDA_ADC_3P3

3.3 V power supply for 12-bit ADC, 600

A typical, 750 A max, for each ADC.

100 Ohm max loading for touch panel,

cause 33 mA current.

NVCC_GPIO

NVCC_SD0

Imax = N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 x F)—Data change rate. Up to 0.5 of the clock rate (F)

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

Table 14. Low power mode current and power consumption

Mode

Test Conditions

Supply

Typical1

Units

SYSTEM IDLE

• LDO_ARM and LDO_SOC set to the Bypass

mode

• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V

• CPU in WFI, CPU clock gated

• 24 MHz XTAL is ON

• System PLL is active, other PLLs are power down

• Peripheral clock gated, but remain powered

DCDC_IN (3.3 V)

VDD_HIGH_IN (3.3 V)

5.2

VDD_SNVS_IN (3.3 V)

0.036

Total

30.479

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