F59L2G81XA datasheet(4/95 Pages) ESMT

4 / 95 page

ESMT

F59L2G81XA (2B)

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul.

2019

Revision: 1.2

4/95

PIN/ BALL NAMES

Pin/ Ball Name

Type

Function

VCC

Supply

NAND Power Supply

VSS

Supply

Ground

I/O0 to I/O7

Input/output

Data inputs/outputs: The I/O0 to 7 pins are used as a port for transferring address, command

and input/output data to and from the device.

ALE

Input

Address latch enable: The ALE signal is used to control loading address information into the

internal address register. Address information is latched into the address register from the I/O

port on the rising edge of WE# while ALE is High.

CLE

Input

Command latch enable: The CLE input signal is used to control loading of the operation mode

command into the internal command register. The command is latched into the command

CE#

Input

Chip enable: The device goes into a low-power Standby mode when CE# goes High during the

device is in Ready state. The CE# signal is ignored when device is in Busy state (R/B# = L),

such as during a Program or Erase or Read operation, and will not enter Standby mode even if

the CE# input goes High.

RE#

Input

Read enable: The RE# signal controls serial data output. Data is available tREA after the falling

edge of RE#. The internal column address counter is also incremented (Address = Address +

l) on this falling edge.

WE#

Input

Write enable: The WE# signal is used to control the acquisition of data from the I/O port.

WP#

Input

Write protect: The WP# signal is used to protect the device from accidental programming or

erasing. The internal voltage regulator is reset when WP# is Low. This signal is usually used

for protecting the data during the power-on/off sequence when input signals are invalid.

R/B#

Output

Ready/busy: The R/B# output signal is used to indicate the operating condition of the device.

The R/B# signal is in Busy state ( R/B# = L) during the Program, Erase and Read operations

and will return to Ready state (R/B# = H) after completion of the operation. The output buffer

for this signal is an open drain and has to be pulled-up to VCC with an appropriate resister. If

R/B# signal is not pulled-up to VCC (“Open” state), device operation can not guarantee.

LOCK

INPUT

When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the

BLOCK LOCK, connect LOCK to VSS during power-up, or leave it disconnected (internal

pull-down).

No connect: NCs are not internally connected. They can be driven or left unconnected.

DNU

Do not use: DNUs must be left unconnected.

NOTE:

See Device and Array Organization for detailed signal connections.

If See Asynchronous Interface Bus Operation for detailed asynchronous interface signal descriptions.

F59L2G81XA Folha de dados(PDF) 4 Page - Elite Semiconductor Memory Technology Inc.

F59L2G81XA Folha de dados(HTML) 4 Page - Elite Semiconductor Memory Technology Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Folha de dados Download

Ligação URL