List of figures

Figure 1.

Pin connections (top view) ............................................................ 2

Figure 2.

Pin connections for each package (top view) ............................................... 3

Figure 3.

Supply current vs. supply voltage ...................................................... 11

Figure 4.

Input offset voltage distribution at VCC = 4 V ............................................... 11

Figure 5.

Input offset voltage distribution at VCC = 12 V .............................................. 11

Figure 6.

Input offset voltage distribution at VCC = 36 V .............................................. 11

Figure 7.

Input offset voltage vs. temperature at VCC = 36 V .......................................... 11

Figure 8.

Input offset voltage temperature variation distribution at VCC = 36 V .............................. 11

Figure 9.

Input offset voltage vs. supply voltage ................................................... 12

Figure 10.

Input offset voltage vs. common-mode voltage at VCC = 4 V .................................... 12

Figure 11.

Input offset voltage vs. common-mode voltage at VCC = 36 V ................................... 12

Figure 12.

Input bias current vs. temperature at VICM = VCC/2 .......................................... 12

Figure 13.

Input bias current vs. common-mode voltage at VCC = 36 V .................................... 12

Figure 14.

Output current vs. output voltage at VCC = 4 V ............................................. 12

Figure 15.

Output current vs. output voltage at VCC = 36 V ............................................ 13

Figure 16.

Output voltage (Voh) vs. supply voltage .................................................. 13

Figure 17.

Output voltage (Vol) vs. supply voltage .................................................. 13

Figure 18.

Negative slew rate at VCC = 36 V ...................................................... 13

Figure 19.

Positive slew rate at VCC = 36 V ....................................................... 13

Figure 20.

Slew rate vs. supply voltage .......................................................... 13

Figure 21.

Bode diagram at VCC = 4 V .......................................................... 14

Figure 22.

Bode diagram at VCC = 36 V ......................................................... 14

Figure 23.

Phase margin vs. output current at VCC = 4 V .............................................. 14

Figure 24.

Phase margin vs. output current at VCC = 36 V ............................................. 14

Figure 25.

Phase margin vs. capacitive load ...................................................... 14

Figure 26.

Overshoot vs. capacitive load at VCC = 36 V............................................... 14

Figure 27.

Small step response vs. time at VCC = 4 V ................................................ 15

Figure 28.

Output desaturation vs. time.......................................................... 15

Figure 29.

Amplifier behavior close to the rails at VCC = 36 V ........................................... 15

Figure 30.

Noise vs. frequency at VCC = 36 V ..................................................... 15

Figure 31.

Noise vs. time at VCC = 36 V ......................................................... 15

Figure 32.

THD+N vs. frequency .............................................................. 15

Figure 33.

THD+N vs. output voltage ........................................................... 16

Figure 34.

PSRR vs. frequency at VCC = 36 V ..................................................... 16

Figure 35.

Channel separation vs. frequency at VCC= 36 V ............................................ 16

Figure 36.

Input current limitation .............................................................. 17

Figure 37.

Stability criteria with a serial resistor at different supply voltages ................................. 19

Figure 38.

Test configuration for Riso ........................................................... 19

Figure 39.

SOT23-5 package outline ........................................................... 21

Figure 40.

MiniSO8 package outline ............................................................ 22

Figure 41.

DFN8 3x3 package outline and mechanical data ............................................ 23

Figure 42.

DFN8 3x3 footprint data............................................................. 24

Figure 43.

SO-8 package outline .............................................................. 25

TSB571, TSB572

List of figures

DS11248 - Rev 7

page 30/31