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STPMIC1 Folha de dados(PDF) 85 Page - STMicroelectronics |
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STPMIC1 Folha de dados(HTML) 85 Page - STMicroelectronics |
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85 / 140 page ![]() 6.3.11 Watchdog timer control register (WDG_TMR_CR) Table 35. WDG_TMR_CR 7 6 5 4 3 2 1 0 WDG_TMR [7:0] R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x1C Type: read/write register Default: 0x00 Description: watchdog timer control register. This register is initialized to default value upon entering CHECK&LOAD state. [7 :0] WDG_TMR[7:0]: watchdog downcounter period value Value in second. 0x00 = 1 s … 0xFF=256 s STPMIC1 Control registers DS12792 - Rev 7 page 85/140 |
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